This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic control system. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.

Recent developments in commutative algebra, linear algebra, and graph theory allow us to approach various issues in several fields. Circulant graphs now have a wider range of practical uses, including as the foundation for optical networks, discrete cellular neural networks, small-world networks, models of chemical reactions, supercomputing and multiprocessor systems. Herein, we are concerned with the decompositions of the bipartite circulant graphs. We propose the Cartesian and tensor product approaches as helping tools for the decompositions. The proposed approaches enable us to decompose the bipartite circulant graphs into many categories of graphs. We consider the use cases of applying the described theory of bipartite circulant graph decomposition to the problems of finding new topologies and deadlock-free routing in them when building supercomputers and networks-on-chip.

Nowadays, the problems of traffic accidents, inefficiency, and congestion still affect transportation systems. Conventional solutions often do not resolve and can even exacerbate the problems. Intelligent transportation system (ITS) technology, including intelligent vehicles, could provide a solution for these problems. However, such technologies should be thoroughly verified and validated before their large-scale adoption. Computer simulation can be used for this task to avoid the expenses of real-world testing. Modern consumer hardware computers are not powerful enough to handle large-scale scenes with high detail. Therefore, a parallel simulation approach employing multiple computers, each processing a separate scene of limited size, is proposed. To define the requirements for a suitable simulation tool, the needs of ITS simulation and Digital Twin technology are discussed, and existing simulation environments suitable for ITS technology verification and validation are evaluated. Further, an architecture for a parallel and multi-level simulation environment for large-scale detailed ITS modeling is proposed. The proposed integrated simulation environment uses the nanoscopic CARLA and microscopic SUMO simulators to implement multi-level and parallel nanoscopic simulation by creating a large scene on the microscopic simulation level and combining the information from multiple parallelly executed nanoscopic scenes. Special handling for nanoscopic scene logic is proposed using a concept of Buffer Zones that allows traffic participants to perceive environmental information beyond the logical boundary of the scene they belong to. The proposed approaches are demonstrated in a series of experiments as a proof of concept and are integrated into the CAVISE simulation environment.

Based on the analysis of a large dataset for optimal undirected double-loop networks, we studied the problem of finding families of optimal double-loop graphs with the minimal possible diameter. Optimal double-loop networks are of practical interest as graph models for reliable, low-delay communication in computer systems and networks-on-chip, due to their advantageous networking properties. A large dataset of optimal double-loop networks with up to 50000 nodes and all the optimal generators for given graph orders were built. We automated the process of searching for analytical (described by polynomials in diameter) descriptions of the families of optimal double-loop networks. After applying the integration of differential evolution methods, exhaustive local search, and a new search algorithm (based on the division of graph description polynomials) to the analysis of the generated dataset, we found a large amount of new (distinct from all previously known) families of optimal double-loop networks with generators of linear or quadratic types. Based on the analysis of the constructed dataset, a method for accelerated search for finding descriptions of optimal double-loop networks using second-order surface approximation was proposed. Our new approach can be used for the analysis of datasets of other promising classes of graphs and networks.

This work is devoted to the development of a single environment for high-level Network-on-Chip (NoC) modeling. The developed environment includes several high-level models and optimization methods. This concept allows for more accurate modeling and reduces simulation time. The concept of the software environment is proposed, and the requirements for added models are described. Methods for optimizing the process of high-level NoC modeling (the comparative method, parallel launch of several models, binary search method, golden section method, similarity method) are developed and tested. Modelling results are studied using the methods proposed.