For a family of optimal two-dimensional circulant networks with an analytical description, two new improved versions of the shortest path search algorithm with a constant complexity estimate are obtained. A simple, based on the geometric model of circulant graphs, proof of the formulas used for the shortest path search algorithm is given. Pair exchange algorithms are presented, and their estimates are given for networks-on-chip (NoCs) with a topology in the form of the considered graphs. New versions of the algorithm improve the previously proposed shortest path search algorithm for optimal generalized Petersen graphs with an analytical description. The new proposed algorithm is a promising solution for the use in NoCs which was confirmed by an experimental study while synthesizing NoC communication subsystems and comparing the consumed hardware resources with those when other previously developed routing algorithms.

This article considers the usage of circulant topologies as a promising deadlock-free topology for networks-on-chip (NoCs). A new high-level model, Newxim, for the exploration of NoCs with any topology is presented. Two methods for solving the problem of cyclic dependencies in circulant topologies, which limit their applications for NoCs due to the increased possibility of deadlocks, are proposed. The first method of dealing with deadlocks is universal and applicable to any topology; it is based on the idea of bypassing blocked sections of the network on an acyclic subnetwork. The second method—Ring-Split—takes into account the features of circulant topologies. The results of high-level modeling and comparison of the peak throughput of NoCs for circulant and mesh topologies using deadlock-free routing algorithms are presented. It was shown that a new approach for routing in circulants (compared to mesh topology) shows up to 59% better network throughput with a uniform distribution of network load.

This work is devoted to the study of application of new topologies in the design of networks-on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC design, and it is developed an optimized routing algorithm with the decreased memory usage. The proposed routing algorithm was compared with Table routing, Clockwise routing, and Adaptive routing algorithms, previously developed for ring circulant topologies, and specialized routing algorithm for multiplicative circulants. The results of synthesis of routers implementing proposed routing algorithms are presented. The cost of ALM and register resources for the implementation of communication subsystems in NoCs with circulant topologies is estimated.

A new pair routing algorithm for transmitting messages in multiprocessor systems and networks-on-chip based on circulant networks of arbitrary dimension is proposed. It allows using all reserve shortest paths in the presence of destructive factors (deadlocks, livelocks, starvation, failures) at the nodes and channels of the communication network. A distinctive feature of the proposed algorithm is the absence of using the routing tables with fixed shortest paths when message is transmitted. It becomes possible to determine the set of the shortest paths for routing due to the relative addresses of destination nodes based on a parametric description of the network. Estimates of the number of reserve shortest paths are obtained, and an effective algorithm for using these paths to prevent dynamic topology changes and network congestions is proposed. To reduce the required memory in networks-on-chip with a circulant topology, we proposed a version of the routing algorithm for two-dimensional optimal circulants. We experimentally found the minimum number of reference nodes (nodes containing mapping tables) for them and estimates of memory for mapping tables, as well as the average path length for the routing algorithm using the reference nodes.

This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic control system. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.

This work includes a review of MIPS architecture processor cores and a review of network topology consisting of routers. It was demonstrated by realization of 2 multiprocessor systems developed on the basis of mesh topology using modified schoolMIPS soft-processor cores, in which architecture additional blocks and instructions were added, and routers with XY routing. As a result, the obtained NoC performance is up to 1.87 Gbit/s (4 processor cores), and up to 1.54 Gbit/s (10 processor cores). The extended processor core schoolMIPS consumes 452 ALMs and 1692 bits of memory; NoC of 4 processor cores takes 2223 ALMs and 9136 bits of memory; NoC of 10 processor cores-5696 ALMs and 22840 bits of memory. The obtained results suggest that there is a possibility of NoC development with the number of nodes up to 200 nodes on Stratix IV GX EP4SGX230 (DE4).