Hybrid bonding technology has recently emerged as a promising solution for advanced semiconductor packaging technologies. However, several reliability issues still pose challenges for commercialization. In this study, we investigated the possibility of crack formation caused by chemical mechanical polishing (CMP) defects and the misalignment of the hybrid bonding structure. Crack formation and thermomechanical stress were analyzed for two common hybrid bonding structures with misalignment using a numerical simulation. The effects of annealing temperature and dishing value on changes in the non-bonding area and peeling stress were systematically analyzed. The calculated peeling stresses were compared to the bonding strength of each bonding interface to find vulnerable regions prone to cracking. The non-bonding area in the bonding structure increased with a decreasing annealing temperature and an increasing dishing value. To achieve a sufficient bonding area of more than 90%, the annealing temperature should be greater than 200 °C. During the heating period of the annealing process, the SiCN-to-SiCN bonding interface was the most vulnerable cracking site with the highest peeling stress. An annealing temperature of 350 °C carries a significant risk of cracking. On the other hand, an annealing temperature lower than 250 °C will minimize the chance of cracking. The SiCN-to-SiO₂ bonding interface, which has the lowest adhesion energy and a large coefficient of thermal expansion (CTE) mismatch, was expected to be another possible cracking site. During cooling, the SiCN-to-Cu bonding interface was the most vulnerable site with the highest stress. However, the simulated peeling stresses were lower than the adhesion strength of the bonded interface, indicating that the chance of cracking during the cooling process was very low. This study provides insights into minimizing the non-bonding area and preventing crack formation, thereby enhancing the reliability of hybrid bonding structures.

The aim of this study was to develop a flexible package technology using laser-assisted bonding (LAB) technology and an anisotropic solder paste (ASP) material ultimately to reduce the bonding temperature and enhance the flexibility and reliability of flexible devices. The heat transfer phenomena during the LAB process, mechanical deformation, and the flexibility of a flexible package were analyzed by experimental and numerical simulation methods. The flexible package was fabricated with a silicon chip and a polyimide (PI) substrate. When the laser beam was irradiated onto the flexible package, the temperatures of the solder increased very rapidly to 220 °C, high enough to melt the ASP solder, within 2.4 s. After the completion of irradiation, the temperature of the flexible package decreased quickly. It was found that the solder powder in ASP was completely melted and formed stable interconnections between the silicon chip and the copper pads, without thermal damage to the PI substrate. After the LAB process, the flexible package showed warpage of 80 μm, which was very small compared to the size of the flexible package. The stress of each component in the flexible package generated during the LAB process was also found to be very low. The flexible device was bent up to 7 mm without failure, and the flexibility can be improved further by reducing the thickness of the silicon chip. The bonding strength and environmental reliability tests also showed the excellent mechanical endurance of the flexible package.

The mechanical reliability of glass substrates is a key challenge for their adoption in advanced semiconductor packaging. This study employs finite element analysis to systematically evaluate the risk of edge crack propagation in large glass panels during redistribution layer (RDL) fabrication. The influence of critical factors—including crack location, number of RDLs, glass material and thickness, dielectric ABF properties, Cu content, and edge clearance—was examined. Results revealed that top-edge crack near the RDL/glass interface pose the highest failure risk due to elevated peeling stress and increased energy release rate (ERR). The risk of propagation intensifies with more RDLs and thinner glass, while high CTE (coefficients of thermal expansion) glasses such as D263, Gorilla, and ceramic glass markedly suppress crack growth compared with borofloat 33 and fused silica. Among ABF dielectrics, GZ-41 demonstrated superior crack resistance owing to its low CTE and moderate stiffness. Although higher Cu content slightly reduced ERR, its effect remained limited. Edge clearance strongly affects reliability, with ≥300 µm providing effective suppression of crack propagation. These findings provide quantitative design guidelines for glass interposer structures, emphasizing the optimization of dielectric material selection, glass substrate and thickness, and layout constraints such as edge clearance. The proposed methodology and results will contribute to establishing reliable strategies for deploying ultra-thin glass panels in advanced semiconductor packaging.

With the increasing complexity and integration density of System-in-Package (SiP) technologies, the demand for selective electromagnetic interference (EMI) shielding is growing. Conventional sputtering processes, while effective for conformal EMI shielding, lack selectivity and often require additional masking or post-processing steps. In this study, we propose a novel, laser-based approach for the selective removal of EMI shielding layers without physical masking. Numerical simulations were conducted to investigate the thermal and mechanical behavior of multilayer EMI shielding structures under two irradiation modes: full-area and laser scanning. The results showed that the laser scanning method induced higher interfacial shear stress, reaching up to 38.6 MPa, compared to full-area irradiation (12.5 MPa), effectively promoting delamination while maintaining the integrity of the underlying epoxy mold compound (EMC). Experimental validation using a nanosecond pulsed fiber laser confirmed that complete removal of the EMI shielding layer could be achieved at optimized laser powers (~6 W) without damaging the EMC, whereas excessive power (8 W) caused material degradation. The laser scanning speed was 50 mm/s, and the total laser irradiation time of the package was 0.14 s, which was very fast. This study demonstrates the feasibility of a non-contact, damage-free, and selective EMI shielding removal technique, offering a promising solution for next-generation semiconductor packaging.