One of the key components of a chemical gas sensor is a MEMS micro-heater. Micro-heaters are used in both semiconductor gas sensors and NDIR gas sensors; however they each require different heat dissipation characteristics. For the semiconductor gas sensors, a uniform temperature is required over a wide area of the heater. On the other hand, for the NDIR gas sensor, the micro-heater needs high levels of infrared radiation in order to increase sensitivity. In this study, a novel design of a poly-Si micro-heater is proposed to improve the uniformity of heat dissipation on the heating plate. Temperature uniformity of the micro-heater is achieved by compensating for the variation in power consumption around the perimeter of the heater. With the power compensated design, the uniform heating area is increased by 2.5 times and the average temperature goes up by 40 °C. Therefore, this power compensated micro-heater design is suitable for a semiconductor gas sensor. Meanwhile, the poly-Si micro-heater without compensation shows a higher level of infrared radiation under equal power consumption conditions. This indicates that the micro-heater without compensation is more suitable for a NDIR gas sensor. Furthermore, the micro-heater shows a short response time of less than 20ms, indicating a very high efficiency of pulse driving.

The mechanical reliability of glass substrates is a key challenge for their adoption in advanced semiconductor packaging. This study employs finite element analysis to systematically evaluate the risk of edge crack propagation in large glass panels during redistribution layer (RDL) fabrication. The influence of critical factors—including crack location, number of RDLs, glass material and thickness, dielectric ABF properties, Cu content, and edge clearance—was examined. Results revealed that top-edge crack near the RDL/glass interface pose the highest failure risk due to elevated peeling stress and increased energy release rate (ERR). The risk of propagation intensifies with more RDLs and thinner glass, while high CTE (coefficients of thermal expansion) glasses such as D263, Gorilla, and ceramic glass markedly suppress crack growth compared with borofloat 33 and fused silica. Among ABF dielectrics, GZ-41 demonstrated superior crack resistance owing to its low CTE and moderate stiffness. Although higher Cu content slightly reduced ERR, its effect remained limited. Edge clearance strongly affects reliability, with ≥300 µm providing effective suppression of crack propagation. These findings provide quantitative design guidelines for glass interposer structures, emphasizing the optimization of dielectric material selection, glass substrate and thickness, and layout constraints such as edge clearance. The proposed methodology and results will contribute to establishing reliable strategies for deploying ultra-thin glass panels in advanced semiconductor packaging.

In this work, we investigated the failure mechanism of a flip-chip chip size package with a low-k layer using a copper pillar bump by experimental and numerical analysis. We observed damage on the Cu pillar bump process due to excessive induced stress after the chip attach reflow; a feature known as white bump. The maximum tensile stress was concentrated on the Al pad and the interface between the low-k layer and Al pad, which were the possible sites for crack initiation and delamination. In order to prevent the low-k failure, the effects of five parameters on the low-k layer stress were systematically investigated, which were the under bump metallization (UBM) diameter, die thickness, die size, coefficient of temperature expansion (CTE) of the substrate core, and diameter of the solder resist opening. Numerical simulation results indicated that larger UBM, thinner die and lower CTE core materials were beneficial for reducing the stress on the low-k layer. Application of the optimized parameters reduced the low-k layer stress by 50%.