Automatic modulation classification (AMC) is a vital process in wireless communication systems that is fundamentally a classification problem. It is employed to automatically determine the type of modulation of a received signal. Deep learning (DL) methods have gained popularity in addressing the problem of modulation classification, as they automatically learn the features without needing technical expertise. However, their efficacy depends on the complexity of the algorithm, which can be characterized by the number of parameters. In this research, we presented a deep learning algorithm for AMC, inspired by residual learning, which has remarkable accuracy and great representational ability. We also employed a squeeze-and-excitation network that is capable of exploiting modeling interconnections between channels and adaptively re-calibrates the channel-wise feature response to improve performance. The proposed network was designed to meet the accuracy requirements with a reduced number of parameters for efficiency. The proposed model was evaluated on two benchmark datasets and compared with existing methods. The results show that the proposed model outperforms existing methods in terms of accuracy and has up to $72.5\%$ fewer parameters than convolutional neural network designs.

Digit-serial arithmetic has emerged as a viable approach for designing hardware accelerators, reducing interconnections, area utilization, and power consumption. However, conventional methods suffer from performance and latency issues. To address these challenges, we propose an accelerator design using left-to-right (LR) arithmetic, which performs computations in a most-significant digit first (MSDF) manner, enabling digit-level pipelining. This leads to substantial performance improvements and reduced latency. The processing engine is designed for convolutional neural networks (CNNs), which includes low-latency LR multipliers and adders for digit-level parallelism. The proposed DSLR-CNN is implemented in Verilog and synthesized with Synopsys design compiler using GSCL 45nm technology, the DSLR-CNN accelerator was evaluated on AlexNet, VGG-16, and ResNet-18 networks. Results show significant improvements across key performance evaluation metrics, including response time, peak performance, power consumption, operational intensity, area efficiency, and energy efficiency. The peak performance measured in GOPS of the proposed design is 4.37× to 569.11× higher than contemporary designs, and it achieved 3.58× to 44.75× higher peak energy efficiency (TOPS/W), outperforming conventional bit-serial designs.