The device proposed in this paper is Triple Material Gate based Doping less Tunnel Field effect Transistor (TMG DL-TFET) which can be thought of as a potential contender for low power applications and a successor for MOSFET. The paper compares the performance of two Tunnel Field Effect Transistor based devices i.e., Single Material Gate based Doping less TFET (SMG DL-TFET) and Triple Material Gate based Doping less TFET (TMG DL-TFET). The device structure for TMG DL-TFET has been developed by using three different metal work functions at the gate and for SMG DL-TFET; a single metal work function is used. The doping has been eliminated and charge plasma technique is introduced to incite holes and electrons at the source and drain sides respectively. With three different metal work functions at the gate, the TMG DL-TFET showed better analog and radio frequency performance than its Single Material counterpart like improved transconductance (g_m ) (an increase of 56.47%), electrical parameters and unity gain frequency (f_T ) (an increase of 28.57%).

In this paper, a novel low power consumption device based on a dopingless gate-all-around nanowire tunnel field effect transistor (TFET) with negative capacitance (NC) effect is proposed. NC is a robust approach in solving the bottleneck issues encountered by devices operating in nanoscale domains. Additionally, the threshold voltage ( V _T ) and subthreshold swing (SS) are dropped significantly to less than 60 mV/decade. Negative capacitance makes a significant contribution to the device’s performance by lowering the operating voltage for low-power applications. To calculate the optimum bias, the Landau–Khalatnikov (L–K) equation was used. To evaluate the influence of NC, the ferroelectric (FE) material PZT (lead zirconate titanate), which has perovskite properties, was used as a gate insulator. Thus, the gate-all-around dopingless nanowire TFET (GAA DL NW TFET) device structure is reconfigured into GAA NC DL NW TFET. PZT has an appropriate polarization rate, high dielectric capacitance, and a high degree of reliability. To achieve an SS lower than 60 mV/decade at lower V _T , effective tuning of the FE thickness is critical to avoid hysteresis, which enhances the overall performance of the proposed device. The aggressively scaled device has the problem of fabrication complexity and its associated cost that is addressed with the help of the dopingless technique to the nanowire-based TFET. The enhancement of the ON-current with an improved steep SS was addressed. With the application of the NC technique, the proposed device showcased an improved 4 µ A µ m ⁻¹ of I _ON , and 10 ¹² of current ratio. Additionally, the influence of the variation in FE thickness on the performance parameters is examined. The proposed device structure operates at a minimum operating voltage, making it an ideal choice for low-power voltage applications.

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications.

The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal oxide thin-film transistors and p-type organic thin-film transistors offers a potential solution. However, increasing the transistor density of these systems through vertical stacking is challenging due to issues related to thermal budget and interface roughness. Here we report a six-stack hybrid complementary transistor technology that has 41 layers and uses n-type indium oxide (In ₂ O ₃ ) and a p-type organic semiconductor (C16IDT-BT) as channel materials. We test 600 transistors and show that n-type oxide devices and p-type organic devices exhibit comparable field-effect mobilities and saturation currents. We also create 300 hybrid inverters by integrating the oxide and organic transistors; the circuits exhibit a gain of 94.84 V V ⁻¹ and a power consumption of 0.47 µW. We also fabricate NAND and NOR gates comprising transistors from four stacks. Thermal stability analysis shows that device characteristics begin to degrade above 50 °C, a known limitation of low-thermal-budget processes. Such performance is sufficient for many large-area electronics applications, but further thermal optimization will be necessary to extend operational robustness towards standard industrial conditions.