This paper reviews the state of the arts and trends of the AI-based biomedical processing algorithms and hardwares. The algorithms and hardwares for different biomedical applications such as ECG, EEG and hearing aid have been reviewed and discussed. For algorithm design, various widely used biomedical signal classification algorithms have been discussed including support vector machine (SVM), back propagation neural network (BPNN), convolutional neural networks (CNN), probabilistic neural networks (PNN), recurrent neural networks (RNN), Short-term Memory Network (LSTM), fuzzy neural network and etc. The pros and cons of the classification algorithms have been analyzed and compared in the context of application scenarios. The research trends of AI-based biomedical processing algorithms and applications are also discussed. For hardware design, various AI-based biomedical processors have been reviewed and discussed, including ECG classification processor, EEG classification processor, EMG classification processor and hearing aid processor. Various techniques on architecture and circuit level have been analyzed and compared. The research trends of the AI-based biomedical processor have also been discussed.

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 μm show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3×, 19×, 29× respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations.

In emerging Spiking Neural Network (SNN) based neuromorphic hardware design, energy efficiency and on-line learning are attractive advantages mainly contributed by bio-inspired local learning with nonlinear dynamics and at the cost of associated hardware complexity. This paper presents a novel SNN design employing fast COordinate Rotation DIgital Computer (CORDIC) algorithm to achieve fast spike timing–dependent plasticity (STDP) learning with high hardware efficiency. In this study, a system design and evaluation method of CORDIC-based SNN is proposed for finding optimal CORDIC type and precision, from theoretical CORDIC-level error to application-level learning performance. From the proposed design and evaluation method, a reconfigurable SNN design based on fast-convergence CORDIC is designed to achieve high classification accuracy on MNIST, fast on-line learning and good energy efficiency. By utilizing SNN’s fault tolerance and time-division-multiplexing (TDM) strategy, the reconfigurable SNN design employs 8-bit fast-convergence CORDIC and TDM-based hardware accelerator for high efficiency. FPGA implementation results confirm that the proposed fast-convergence CORDIC SNN design outperforms the state-of-the-art CORDIC method by 38.5%−45.3% in terms of learning speed and energy efficiency, with the STDP learning of 30.2 ns/SOP, energy efficiency of 176.6 pJ/SOP, processing speed of 6.1 ms/image, and on-line learning convergence of 21.4 s (time to reach the final accuracy, on average), on MNIST benchmark.

Entropy is a measure of uncertainty or randomness. It is the foundation for almost all cryptographic systems. True random number generators (TRNGs) and physical unclonable functions (PUFs) are the silicon primitives to respectively harvest dynamic and static entropy to generate random bit streams. In this survey paper, we present a systematic and comprehensive review of different state-of-the-art methods to harvest entropy from silicon-based devices, including the implementations, applications, and the security of the designs. Furthermore, we conclude the trends of the entropy source design to point out the current spots of entropy harvesting.

With the rapid development of semiconductor technologies, the wideband transceiver is in the trend to be integrated on-chip with compact size and low power consumption. This survey investigates the integrated wideband chip-scale RF transceivers for radar applications including imaging, multimodal sensing, and recognition on gaits, where frequency modulated continuous wave (FMCW) radar sensors are investigated in detail. Besides radar sensing, integrated wideband RF transceivers for accurate localization and efficient communications with spectrum sharing are discussed, in which the integrated wideband transceiver techniques for ultra-wideband (UWB) communications are highlighted. The compact and efficient antenna designs for integrated wideband RF transceivers are discussed. Furthermore, leveraging the artificial intelligence (AI)-enhanced signal processing techniques, edge devices with energy-efficient integrated RF transceivers can ensure precise localization and realize versatile sensing to empower accurate health status monitoring, intelligent robots, gesture recognition, and enhanced communications. We envisioned the future integrated wideband RF transceiver development trends, where the promising tera-Hertz (THz) integrated transceiver techniques are discussed. Notably, the wideband integrated RF transceiver technique is promising to enable efficient, flexible, and seamless communications and sensing for the future-generation intelligent Internet of Everything (IoE) applications.

This paper presents a built-in self test (BIST) methodology, architecture and circuits for testing Through Silicon Vias (TSVs) in 3D-IC systems prior to stacking in order to improve 3D-IC yield and reduce overall test cost. A scan switch network (SSN) architecture is proposed to perform pre-bond TSV scan testing in test mode, and operate as functional circuit in functional mode, respectively. In the SSN, novel test structures and circuits are proposed to address pre-bond TSV test accessibility issue and perform stuck-at-fault tests and TSV tests. By exploiting the inherent RC delay characteristics of TSV, a novel delay-based TSV test method is also proposed to map the variation of TSV-to-substrate resistance due to TSV defects to a test path delay change. Compared with state-of-art methods, the proposed BIST methodology addresses pre-bond TSV testing with a low-overhead integrated test solution which is compatible to existing 2D-IC testing method. The proposed BIST architecture and method can be implemented by standard DFT design flow and integrated into a unified pre-bond TSV test flow. Experiment results and robustness analysis are presented to verify the effectiveness of the proposed self-test methodology, architecture, and circuits.