Jianquan Jia

Mr. Jianquan Jia


Research Focus & Metrics

Academic Career Length

10Years (2017-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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9 August 2017 in Instruments
Verified
Journal Article
Open access
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JJJiang Jiali
Jiang Jiali
JJJianquan Jia
Jianquan Jia
TZTianqi Zhao
Tianqi Zhao
KLKun Liang
Kun Liang
RYRu Yang
Ru Yang
DHDejun Han
Dejun Han
The silicon photomultiplier (SiPM) is a promising semiconductor device for low-level light detection. The recovery time, or the photon-counting rate of the SiPM is essential for high-flux photon detection in such applications as photon counting computer tomography (CT). A SiPM with epitaxial quenching resistors (EQR SiPM) has advantages in fabricating small APD microcells connected in series with lower quenching resistors, therefore, APD cells with a low RC time constant and a short recovery time can be expected. In this report, the recovery time of EQR SiPM has been investigated using both the double light pulse method and the waveform analysis method. The results show that the recovery time of EQR SiPM is strongly dependent on the size of the active area and the number of fired pixels. For a 3 × 3 mm2 device, while total about 90,000 pixels were fired, the recovery time was 31.1 ± 1.8 ns; while fired pixels were controlled to about 2000, the recovery time decreased significantly to 6.5 ± 0.4 ns; and the recovery time of one fired pixel was 3.1 ± 0.2 ns. For 1.4 × 1.4 mm2 device, the recovery time was 15.2 ± 0.5 ns, while a total of about 20,000 pixels were fired. Effects that may affect the recovery time of the SiPM, including strength of the pulse light, signal transmission time delay, and the readout electronics are discussed.

17 September 2023 in Micromachines
Verified
Journal Article
Open access
PDF file
JJJianquan Jia
Jianquan Jia
LJLei Jin
Lei Jin
KYKaikai You
Kaikai You
AZAnyi Zhu
Anyi Zhu
Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug‘s N-type doping scheme is proposed to avoid the current dropping anomaly.