As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (vertical and lateral charge loss) was studied in this work. According to experimental analysis and TCAD simulation, it is found that, in vertically scaled 3D NAND, the vertical charge loss is deteriorated not only by the cycling induced tunnel oxide degradation (introducing interface/oxide traps), but also by the cycling induced intercell trapped charge (enhancing word-lines edge electric field), on account of the enhanced Poole-Frenkel effect and tunneling effect. On the other hand, the cycling induced intercell trapped charge can also suppress lateral charge migration. Therefore, the vertical charge loss, rather than the lateral charge migration, still can be the dominant factor for post-cycling retention characteristics in scaling Lg/Ls 3D NAND flash memory.

With gate length (Lg) and gate spacing length (Ls) shrinkage, the cell-to-cell z-interference phenomenon is increasingly severe in 3D NAND charge-trap memory. It has become one of the key reliability concerns for 3D NAND cell scaling. In this work, z-interference mechanisms were investigated in the programming operation with the aid of Technology Computer-Aided Design (TCAD) and silicon data verification. It was found that the inter-cell trapped charges are one of the factors causing z-interference after cell programming, and these trapped charges can be modulated during programming. Thus, a novel program scheme is proposed to suppress the z-interference by reducing the pass voltage (Vpass) of the adjacent cells during programming. As a result, the proposed scheme suppresses the Vth shift of 40.1% for erased cells with Lg/Ls = 31/20 nm. In addition, this work further analyzes the optimization and balance of program disturbance and z-interference with the scaling of cell Lg-Ls based on the proposed scheme.

Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND flash 1-4, and the IVS improvement by re-program scheme was reported. In this work, it is found that re-program can suppress 81% of IVS in 3D NAND, which is much more significant than that of 2D NAND 50 The mechanisms of IVS improvement by re-program scheme in 3D NAND are investigated. Both vertical de-trapping in the BE-tunneling oxide and charge lateral migration (LM) in the charge-trap layer are suppressed in re-program. Re-program is effective in vertical de-trapping suppression both in checker-board pattern (C/P) and solid-board pattern (S/P) cases, and is effective in LM suppression only in C/P case. Furthermore, the LM improvement by re-program scheme is more pronounced with gate length (Lg) and inter-gate space (Ls) scaling down, showing potential in the reliability improvement of advanced 3D NAND technologies.

The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (V_db) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of V_db (V_{db_max}), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of V_{db_max} and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.

Dual-deck stacking technology is an effective solution for solving the contradiction between the demand for increasing storage layers and the challenge of the deep hole etching process in 3D NAND flash. The connection scheme between decks is a key technology for the dual-deck structure. It has become one of the necessary techniques for 3D NAND flash storage density improvement. This article mainly studies the impact of connection schemes between decks on cell reliability. Based on experimental data and simulation analysis, unfavorable effects were found as the gate channeling the breakdown and data retention characteristics of the top cells in the lower deck deteriorated due to the local electric field enhancement in the connection scheme without a poly-plug. This mainly contributed to the structural change of these cells within process impact. They will suffer secondary etching during the upper deck channel etching process due to alignment issues between the upper and lower decks. In another scheme with a poly-plug connection between decks, the saturation current of the channel decreased and the current variation increased. The fundamental cause of the current anomaly is that the Poly-plug has a certain shielding effect on channel inversion and the weak inversion region becomes a bottleneck for the channel current. The increase in variation is due to the shielding effect differences in the different structures of the poly-plug. Therefore, for the connection scheme without a poly-plug, the article proposes to improve device reliability by increasing the oxide thickness between decks and setting the top cells of the lower decks to be virtual cells. For the connection scheme with a poly-plug, the plug‘s N-type doping scheme is proposed to avoid the current dropping anomaly.