In-depth understanding of the pollution problems such as dry bands and the polymeric aging process requires better determination of electric field strength and its distribution over the polymeric surface. To determine the electric field distribution over the insulator surface, this research proposes utilizing a novel approach model based on nonlinear electrical characteristics derived from experimental results for polluted polymer insulators. A case study was carried out for a typical 11 kV polymeric insulator to underline the merits of this new modeling approach. The developments of the proposed pollution model and the subsequent computational works are described in detail. The study is divided into two main stages; laboratory measurements and computer simulations. In the first stage, layer conductance tests were carried out to develop nonlinear field-dependent conductivity for the pollution modeling. In the second part, equipotential and electric field distributions along the leakage were computed using the finite element method (FEM). Comparative field studies showed that the simulation using the proposed dynamic pollution model results in more detailed and realistic field profiles around insulators. This may be useful to predict the formation of dry bands and the initiation of electrical discharges on the polymeric surface.

In Very Large-Scale Integration (VLSI) design, minimizing area and optimizing device performance have become paramount as traditional MOSFET scaling approaches fundamental limits. Energy efficiency is now a primary goal due to MOSFET scaling challenges. Multi-valued logic (MVL), such as quaternary (2-bit) logic, offers a potential solution by increasing information density and reducing interconnect complexity. However, implementing four discrete voltage levels in quaternary logic requires novel device technologies. This work explores Spatial Wavefunction Switched FET (SWS-FET) devices – quantum well transistors enabling multi-state carrier transport – as a size- and power-efficient platform for quaternary logic. We present the development of complementary n-channel and p-channel SWS-FETs to encode the four logic states (00, 01, 10, 11). The proposed SWS-FET quaternary logic gate circuits are designed and simulated using an 180nm CMOS-compatible device model. The accuracy of the SWS-FET circuits is verified in Cadence Virtuoso using a combination of the industry-standard BSIM transistor model and an analog behavioral model (ABM) to capture multi-threshold behavior. Circuit simulations of the 2-bit NOR gate demonstrate that using SWS-FETs reduces transistor count by approximately 42% compared to an equivalent CMOS implementation and by up to 68% compared to current-mode MVL designs. These gains are achieved with low power dissipation and competitive switching speeds, highlighting the promise of SWS-FET technology for energy-efficient multi-valued logic design.