This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[ ]dB, 250[ ]MHz unity gain bandwidth amplifier has been developed in 65[ ]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[ ][ ]A from a 1.2[ ]V supply and occupies the 2184[ ][ ]m² area.

A transformer-less Buck-Boost direct current–direct current (DC–DC) converter in use for the fast charge of electric vehicles, based on powerful high-voltage isolated gate bipolar transistor (IGBT) modules is analyzed, designed and experimentally verified. The main advantages of this topology are: simple structure on the converter’s power stage; a wide range of the output voltage, capable of supporting contemporary vehicles’ on-board battery packs; efficiency; and power density accepted to be high enough for such a class of hard-switched converters. A precise estimation of the loss, dissipated in the converter’s basic modes of operation Buck, Boost, and Buck-Boost is presented. The analysis shows an approach of loss minimization, based on switching frequency reduction during the Buck-Boost operation mode. Such a technique guarantees stable thermal characteristics during the entire operation, i.e., battery charge cycle. As the Buck-Boost mode takes place when Buck and Boost modes cannot support the output voltage, operating as a combination of them, it can be considered as critically dependent on the characteristics of the semiconductors. With this, the necessary duty cycle and voltage range, determined with respect to the input-output voltages and power losses, require an additional study to be conducted. Additionally, the tolerance of the applied switching frequencies for the most versatile silicon-based powerful IGBT modules is analyzed and experimentally verified. Finally, several important characteristics, such as transients during switch-on and switch-off, IGBTs’ voltage tails, critical duty cycles, etc., are depicted experimentally with oscillograms, obtained by an experimental model.

This paper presents a novel low power, low voltage CMOS bandgap reference (BGR) that overcomes the problems with the existing BJT-based reference circuits by using a MOS transistor operating in sub-threshold region. A proportional to absolute temperature (PTAT) voltage is generated by exploiting the self-bias cascode branch, while a Complementary to Absolute Temperature (CTAT) voltage is generated by using the threshold voltage of the transistor. The proposed circuit is implemented in 65[ ]nm CMOS technology. Post-layout simulation results show that the proposed circuit works with a supply voltage of 0.55[ ]V, and generates a 286[ ]mV reference voltage with a temperature coefficient of 59[ ]ppm/^∘C. The circuit takes 413[ ]nA current from 0.55[ ]V supply and occupies 0.00986[ ]mm² of active area.

A subthreshold MOS-based pseudo-resistor featuring a very high value and ultra-low distortion is proposed. A bandpass neural amplifier with a very low high-pass cutoff frequency is designed, to demonstrate the linearity of the proposed resistor. A BJT less CTAT current generator has been introduced to minimize the temperature drift of the resistor and make tuning easier. The standalone resistor has achieved 0.5% better linearity and a 12% improved temperature coefficient over the existing architectures. A neural amplifier has been designed with the proposed resistor as a feedback element. It demonstrated 31$$ dB mid-band gain and a low-pass cutoff frequency of 0.85$$ Hz. The circuit operates from a 1$$ V supply and draws 950$$ nA current at room temperature.

In this paper, a low voltage bandgap reference circuit has been proposed. The introduction of a modified beta multiplier bias circuit decreased the mismatch caused by the PMOS transistors opamp contribution. By shifting the fixed resistors to the NMOSs drain side, the beta multiplier bias minimised threshold mismatch between the two NMOS transistors. A 200-point MC simulation showed a 0.9 mV standard deviation, with a 0.34% accuracy. The simulated temperature coefficient was 64 ppm/⁰C. The proposed circuit consumed 5.04 µW of power from a 0.45 V power supply voltage. A prototype was implemented in 65 nm CMOS technology occupying a 2888 µm² silicon area, with the nominal value of the reference at 261 mV.

A critical review of the Miller compensation technique for a two-stage operational amplifier (op-amp) is presented in this paper. The trade-offs involved in the compensation capacitor value and the small signal parameters of the op-amp are also considered in this paper; that is, the second stage requires a higher bias current, while driving a large capacitive load for a given phase-margin. A technique is presented with a view to increase the g m of the second stage without increasing the power dissipation, hence improving the phase margin while maintaining the unity gain bandwidth (UGB) of the op-amp. A prototype has been designed in 65nm CMOS technology and post-layout simulations exhibit good performance characteristics of 45MHz UGB with 250fF compensation capacitor, for a supply voltage of 1.2V, and a current consumption of $132\boldsymbol{\mu} \mathbf{A}$ . The new technique shows a superior performance to those obtained with an established compensation technique that achieves a 10MHz UGB while dissipating the same power. The total circuit size is 0.00234mm2 silicon area.