Sang Yoon Park

Dr. Sang Yoon Park

Associate Professor, Department of Electronic Engineering, Myongji University, Yongin 17058, South Korea
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Research Focus & Metrics

Academic Career Length

12Years (2015-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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24 February 2021 in IEEE Access
Verified
Journal Article
Open access
SCSu Min Cho
Su Min Cho
PMPramod Meher
Pramod Meher
LTLuong Tran Nhat Trung
Luong Tran Nhat Trung
HCHyo Jin Cho
Hyo Jin Cho
SPSang Yoon Park
Sang Yoon Park
In this paper, we propose a new hardware architecture of a very high-speed finite impulse response (FIR) filter using fine-grained seamless pipelining. The proposed full-parallel pipeline FIR filter can produce an output sample in a few gate delays by placing the pipeline registers not only in between components, but also across the components. A precise critical path analysis at the gate level allows to create an appropriate pipelining strategy depending on the throughput requirement. This paper also presents two alternative architectures, each offering different trade-offs in terms of area and throughput rate. The proposed FIR filters are synthesized to measure the maximum throughput and the balance between complexity and speed. The synthesis results show that the proposed fully pipelined FIR filter supports up to throughput of 1.8 Giga samples per second and offers 73.5% less area-delay product (ADP) than the existing systolic designs. Also, the proposed single multiplier-accumulator (MAC) based FIR filter has 3 times higher throughput and 26.0% less area with 75.8% less ADP compared to the existing design.

19 October 2022 in IEEE Access
Verified
Journal Article
Open access
DHDuc N. M. Hoang
Duc N. M. Hoang
JRJong Myung Rhee
Jong Myung Rhee
SPSang Yoon Park
Sang Yoon Park
Mobile ad hoc networks (MANETs) are particularly suited for scenarios that demand rapid deployment of a communication system without any existing network resources. For instance, a MANET can facilitate the intercommunication process between members of a rescue party in a natural disaster, where the underlying routing protocol is crucial to maintaining the dissemination capability of data-critical packets. However, the backbone of every MANET, i.e., their routing protocol, is limited by the communication range of nodes, their high-speed mobility, and the capacity constraints of energy. This study proposed a fault-tolerant ad hoc on-demand routing protocol (FT-AORP) that relies on these characteristics of MANET nodes to determine reliable paths for data transmission. Subsequently, two of the discovered paths were used to transmit the duplicates of an original data packet to maximize fault tolerance. Further, using the OMNeT++ network simulator, the performance of the proposed system was evaluated through extensive simulation experiments against three simulation parameters: the number of network nodes, node speed, and data packet sending rate. The simulation results demonstrated that FT-AORP greatly improved the packet delivery ratio, reduced end-to-end delay, and maintained a higher residual energy level of the transmission path, compared to other baseline routing protocols.

24 March 2022 in IEEE Access
Verified
Journal Article
Open access
SLSun Sik Lee
Sun Sik Lee
TNThanh Dat Nguyen
Thanh Dat Nguyen
PMPramod Meher
Pramod Meher
SPSang Yoon Park
Sang Yoon Park
Convolutional Neural Network (CNN) plays an important role in several machine learning tasks related to speech, image, and video processing applications. The increasing demand for faster processing in real-time applications requires high-speed implementation of CNN. However, in general, CNN involves higher latency due to the computationally intensive behavior of the convolutional layer. While state-of-the-art architecture provides efficient dataflow of the convolutional operations, this paper proposes a hardware-efficient, high-speed convolution block for ASIC implementation of the CNN algorithm. The proposed convolution block is designed using a novel bit-level-multiply-accumulator (BLMAC) with a modified Booth encoder and a Wallace reduction tree. The critical path of the overall architecture is significantly shortened due to the time-optimized implementation of the proposed BLMAC, which is a main component of the convolution process. Critical path analysis and dataflow strategy are also provided to demonstrate the acceleration of the proposed design. The proposed architecture was synthesized using Synopsys Design Compiler to prove its accelerated processing. The ASIC synthesis results of the proposed architecture using a 65nm standard cell library show at least 53% reduction in latency, 52.2% reduction in area-delay product, and 54.2% reduction in power-delay product compared to the state-of-the-art architecture.

29 March 2019 in Electronics
Verified
Journal Article
Open access
PDF file
PMPramod Meher
Pramod Meher
SPSang Yoon Park
Sang Yoon Park
A conventional coordinate rotation digital computer (CORDIC) has a low throughput rate due to its recursive implementation of micro-rotations. On the contrary, a fully-pipelined cascaded CORDIC provides a very high throughput rate at the cost of high complexity and large area. In this paper, possible design choices of cascaded CORDIC are explored over a wide range of operating frequencies, throughput rates, latency, and area complexity. For this purpose, we present a fine-grained critical path analysis of the cascaded CORDIC in terms of bit-level delay. Based on the propagation delay estimate, we propose an algorithm for determining the required number of pipeline stages and locations of the pipeline registers in order to meet the time constraint in a particular application. A hybrid cascaded-recursive CORDIC is also proposed to increase the throughput rate, and to reduce the latency and energy per sample (EPS). From synthesis results, we show that the proposed pipelined cascaded CORDIC with only four pipeline stages requires 31.1% less area and 29.0% less EPS compared to a fully-pipelined CORDIC. An eight stage pipelined recursive cascaded CORDIC provides 18.3% less EPS and 40.4% less area-delay product than a conventional CORDIC.

5 June 2015 in Scientific Reports
Verified
Journal Article
Open access
PDF file
JPJi-Won Park
Ji-Won Park
HJHyobin Jeong
Hyobin Jeong
BKByeongsoo Kang
Byeongsoo Kang
SKSu Jin Kim
Su Jin Kim
SPSang Yoon Park
Sang Yoon Park
TLTae Geol Lee
Tae Geol Lee
Time-of-flight secondary ion mass spectrometry (TOF-SIMS) emerges as a promising tool to identify the ions (small molecules) indicative of disease states from the surface of patient tissues. In TOF-SIMS analysis, an enhanced ionization of surface molecules is critical to increase the number of detected ions. Several methods have been developed to enhance ionization capability. However, how these methods improve identification of disease-related ions has not been systematically explored. Here, we present a multi-dimensional SIMS (MD-SIMS) that combines conventional TOF-SIMS and metal-assisted SIMS (MetA-SIMS). Using this approach, we analyzed cancer and adjacent normal tissues first by TOF-SIMS and subsequently by MetA-SIMS. In total, TOF- and MetA-SIMS detected 632 and 959 ions, respectively. Among them, 426 were commonly detected by both methods, while 206 and 533 were detected uniquely by TOF- and MetA-SIMS, respectively. Of the 426 commonly detected ions, 250 increased in their intensities by MetA-SIMS, whereas 176 decreased. The integrated analysis of the ions detected by the two methods resulted in an increased number of discriminatory ions leading to an enhanced separation between cancer and normal tissues. Therefore, the results show that MD-SIMS can be a useful approach to provide a comprehensive list of discriminatory ions indicative of disease states.

25 July 2017 in Sensors
Verified
Journal Article
Open access
PDF file
NTNguyen Xuan Tien
Nguyen Xuan Tien
SKSemog Kim
Semog Kim
JRJong Myung RHEE
Jong Myung RHEE
SPSang Yoon Park
Sang Yoon Park
Fault tolerance has long been a major concern for sensor communications in fault-tolerant cyber physical systems (CPSs). Network failure problems often occur in wireless sensor networks (WSNs) due to various factors such as the insufficient power of sensor nodes, the dislocation of sensor nodes, the unstable state of wireless links, and unpredictable environmental interference. Fault tolerance is thus one of the key requirements for data communications in WSN applications. This paper proposes a novel path redundancy-based algorithm, called dual separate paths (DSP), that provides fault-tolerant communication with the improvement of the network traffic performance for WSN applications, such as fault-tolerant CPSs. The proposed DSP algorithm establishes two separate paths between a source and a destination in a network based on the network topology information. These paths are node-disjoint paths and have optimal path distances. Unicast frames are delivered from the source to the destination in the network through the dual paths, providing fault-tolerant communication and reducing redundant unicast traffic for the network. The DSP algorithm can be applied to wired and wireless networks, such as WSNs, to provide seamless fault-tolerant communication for mission-critical and life-critical applications such as fault-tolerant CPSs. The analyzed and simulated results show that the DSP-based approach not only provides fault-tolerant communication, but also improves network traffic performance. For the case study in this paper, when the DSP algorithm was applied to high-availability seamless redundancy (HSR) networks, the proposed DSP-based approach reduced the network traffic by 80% to 88% compared with the standard HSR protocol, thus improving network traffic performance.