A single-photon avalanche diode (SPAD) is a photon-counting sensor renowned for its exceptional single-photon sensitivity. One significant feature of SPADs is their non-linear response to light, making them ideal for high-dynamic range imaging applications. In SPAD imaging, the photon detection mode, which depends on the quenching method employed, is crucial for optimizing image quality and dynamic range. This paper examines the free-running and gating imaging modes, evaluating their impacts on photon capture and saturation limits. Given that the number of incident photons follows a Poisson distribution, we introduce an innovative imaging-quenching model based on statistical mathematics. We designed and fabricated two SPAD imaging sensors using 180 nm CMOS technology. Image processing and evaluation were conducted using a mapping method. Our results show that in low-light conditions, the gating mode surpasses the free-running mode in the signal-to-noise ratio (SNR). However, the free-running mode exhibits a saturation limit of more than an order of magnitude higher than that of the gating mode, demonstrating its superior capability to handle a broader range of light intensities. This paper provides a thorough analysis of the differences between the two imaging methods, incorporating the theoretical mathematical model, circuit characteristics, and computed imaging quality.

In this paper, we propose a novel kind of time delay integration (TDI) image sensor based on single photon avalanche diode (SPAD), i.e. TDI-SPAD. Compared with existing TDI imaging devices, the proposed TDI-SPAD sensor is characterized by low noise, high sensitivity, high modulation transfer function (MTF) and transfer efficiency. The proposed architecture design of multi-stages TDI-SPAD sensor and the digital transfer circuits are discussed in detail, and the full function of TDI-imaging is demonstrated with experiments based upon two SPAD sensors. First, the imaging function of TDI-SPAD is verified through imaging of scanning scene with a 128 × 128 SPAD array. Then, we fabricate a 256 × 2 TDI-SPAD sensor, build a TDI-imaging camera system, and demonstrate the feasibility and SNR improvement of the proposed TDI-imaging sensor.

Single-photon avalanche diodes (SPADs) are novel image sensors that record photons at extremely high sensitivity. To reduce both the required sensor area for readout circuits and the data throughput for SPAD array, in this paper, we propose a snapshot compressive sensing single-photon avalanche diode (CS-SPAD) sensor which can realize on-chip snapshot-type spatial compressive imaging in a compact form. Taking advantage of the digital counting nature of SPAD sensing, we propose to design the circuit connection between the sensing unit and the readout electronics for compressive sensing. To process the compressively sensed data, we propose a convolution neural-network-based algorithm dubbed CSSPAD-Net which could realize both high-fidelity scene reconstruction and classification. To demonstrate our method, we design and fabricate a CS-SPAD sensor chip, build a prototype imaging system, and demonstrate the proposed on-chip snapshot compressive sensing method on the MINIST dataset and real handwritten digital images, with both qualitative and quantitative results.

The SPAD-based 3D dToF image sensor boasts a wide range of applications, attributed by its excellent photon sensitivity. However, increasing the number of time-to-digital converters (TDCs) per pixel does not necessarily enhance measurement efficiency, as photon throughput is limited by readout bandwidth. Moreover, an immense volume of TDC data put the readout circuit under enormous press. A $\mathbf{128}\times \mathbf{128}$ pixels image sensor with an integrated pseudo-event driven readout circuit and 8-bit shared TDC which is designed and fabricated in 180-nm CMOS technology is demonstrated for the ability of reducing data scale and increasing read bandwidth effectively. The proposed pseudo-event driven circuit substantially diminishes the amount of readout data, achieving 94% reduction in data volume at point rate 3%. The chip is capable of both grayscale and depth imaging paired with an area array laser, offering 3 cm accuracy and a maximum range of up to 200 m.

Random numbers play a vital role in modern information security, where quantum random number generators (QRNGs) based on single-photon avalanche diodes (SPADs) offer a promising physical platform for quantum random-number generation. However, practical SPAD QRNGs can exhibit temporal correlation arising from finite photon-event statistics and detector nonidealities. To overcome these limitations, this paper presents a high-speed, 256-channel SPAD QRNG chip, featuring a 256 × 512-pixel array integrated with a rolling-sampling time-division multiplexing architecture. By virtue of the rolling-sampling mechanism, the single-pixel sampling interval is extended to 40.96 μs, which substantially reduces the measured temporal correlation by increasing the per-pixel revisit interval while preserving aggregate throughput. Within one complete operating cycle, the chip generates 256 random bits simultaneously, achieving a maximum aggregate raw output bitrate of 3.2 Gb/s without digital post-processing. An FPGA-based test platform was constructed for experimental verification. Measurements demonstrate that under standard indoor illumination (8 W/m²), the generated raw bitstreams pass all 15 NIST SP 800–22 statistical randomness tests at 3.2 Gb/s without post-processing. Furthermore, under controlled 530 nm illumination, the measured lag-1 serial autocorrelation coefficient decreases below the 10⁻³ reference level at an incident optical power of 11.6 μW. The proposed chip offers a low-optical-power, high-throughput solution for integrated hardware security.