This paper presents a fully integrated high-frequency (HF) radio-frequency identification (RFID) tag chip based on the ISO/IEC 15693 and discusses a series of design techniques, including analog and digital control circuits. In order to get a more coupled power supply, an amplitude shift keying demodulator with very low modulation index is proposed. Moreover, modulator, limiter, and electrostatic discharge circuit are mentioned to make the tag IC work effectively and reliably. Besides, digital control circuit with 2-kbit EEPROM memory is designed to help the tag operate correctly under a very low magnetic field. The proposed RFID tag IC was fabricated using a 0.18-μm 2P6M CMOS technology with an area of 926 μm by 855 μm and a power consumption of less than 120 μA. Data rates of 6.62-52.97 kb/s are supported. The tag can operate under a minimum magnetic field of 0.12 A/m and a minimum modulation index of 2.33% which is far less than 10% required by the RFID standard. Compared with the prior references, the proposed tag IC has better performances especially in the aspect of low modulation index.

The Internet of Things requires greater attention to the security and privacy of the network. Compared to other public-key cryptosystems, elliptic curve cryptography can provide better security and lower latency with shorter keys, rendering it more suitable for IoT security. This paper presents a high-efficiency and low-delay elliptic curve cryptographic architecture based on the NIST-$p_{256}$ prime field for IoT security applications. A modular square unit utilizes a fast partial Montgomery reduction algorithm, demanding just a mere four clock cycles to complete a modular square operation. The modular square unit can be computed simultaneously with the modular multiplication unit, consequently improving the speed of point multiplication operations. Synthesized on the Xilinx Virtex-7 FPGA platform, the proposed architecture completes one PM operation in 0.08 ms using 23.1 k LUTs at 105.3 MHz. These results show significantly better performance compared to that in previous works.

The development and application of various precision electronic devices require a large number of high-precision and low-cost temperature-compensated crystal oscillators (TCXO) to generate frequency references. In order to achieve higher compensation accuracy at lower cost, a new fully integrated analog-TCXO (ATCXO) is proposed in this paper. It uses an innovative temperature-compensated multiplier to generate cubic and quintic voltages. The experimental results show that it can achieve the ultra-high fitting of the frequency-temperature characteristic curve of the crystal. This effectively improves the compensation accuracy of the TCXO. The proposed ATCXO achieves a frequency stability of ± 0.8 ppm in the temperature range of $- 40\,\,^{\circ }\text{C}$ to 95 °C. At the same time, the gain-temperature error of the proposed temperature compensated analog multiplier is $\le 0.13$ dB. This paper is based on SMIC 130 nm process, the core area of the chip is only 0.124 mm2. Multiple modules such as bandgap circuit, n-th power voltage generation circuit, summation circuit, gain control circuit and voltage controlled oscillator using variable capacitor array are integrated.

Turbo code is an error correction coding scheme close to the Shannon limit, usually used in wireless data transmission. Based on the parallel Turbo code algorithm, a parallel Turbo code circuit design scheme is proposed. In the encoder, the recursive systematic convolutional encoder is multiplexed. The decoder is divided into branch metric, recursive, maximum likelihood ratio, and external information calculation modules. The decoding algorithm is based on Max-Log-MAP, controlling the component decoder in parallel. And the state metric calculation in the decoding circuit is combined to reduce the overall power consumption effectively, enabling the encoder and decoder to be used in narrowband Internet of things (NB-IoT). Finally, the hardware scheme of the main functional modules of Turbo code encoding and decoding is designed and implemented. The results show that the dynamic power consumption is less than 50 mW. The overall on-chip power consumption is reduced by 40% at the frequency of 125 MHz compared with previous jobs.

The deployment and application of large-scale Internet of Things require a large number of 13.56-MHz radio-frequency identification (RFID) reader chips with lower cost. The existing RFID reader module needs to integrate multiple chips, such as microcontroller and high-frequency (HF) RFID reader IC on a single printed circuit board (PCB), which has the bottleneck of cost, power consumption, stability, and reliability. In order to adapt to the development trend of high integration, miniaturization, and low-power consumption of RFID reader, this article proposes a fully integrated low-cost RFID reader System-on-a-Chip (SoC), which integrates RF transceiver and analog circuit, baseband protocol processing, microcontroller, memory, and interface circuit into a single chip. The proposed reader IC supports communication protocols, such as ISO/IEC 14443 Type A and Type B, ISO/IEC 15693, and ISO/IEC 7816. The reader can communicate with contact and contactless IC cards. The modulation depth of the transmitter circuit ranges from 1% to 100%, and the maximum transmitting current is 126 mA. The receiver circuit is composed of I/Q clock generation, switched capacitor sampling circuit, variable gain amplifier (VGA) with filter, comparator, and pulse shaping circuit, which has good anti-noise performance. This 13.56-MHz RFID reader SoC is fabricated in a 180-nm CMOS process and is housed in a 64-pin QFP package. The total area is 8.75 mm ² , including 1.47 mm ² for analog and RF circuits.

An NFC tag chip employing the ISO/IEC14443-A protocol is developed in SMIC 0.13 $\upmu$ m EEPROM 2P6M CMOS process, boasting a chip area of 620.03 $\upmu$ m $\times$ 567.93 $\upmu$ m and a power consumption of under 100 $\upmu$ W. The chip addresses critical issues such as reducing power consumption and minimizing area costs for covering numerous IoT nodes. For a small area of the chip, a specialized ESD protection circuit is proposed, efficiently multiplexing discharge transistors, cross-gate connected rectifiers, limiters for overvoltage protection, and load switch modulators within the chip’s limited space. For power efficiency, a compact 175.44 $\upmu$ m $\times$ 32.98 $\upmu$ m 18.52 $\upmu$ A LDO based on the current mirror and current feedback is presented for the DC supply during the 100% ASK modulation. Additionally, an ASK demodulator and a 13.56MHz $\pm$ kHz clock generator are designed in compact areas of 62.19 $\upmu$ m $\times$ 56.06 $\upmu$ m and 24.76 $\upmu$ m $\times$ 13.14 $\upmu$ m, respectively. These components ensure stable protocol communication with digital circuits and support a 7kb EEPROM, providing a comprehensive solution for NFC-based IoT information collection.