The Internet of Things requires greater attention to the security and privacy of the network. Compared to other public-key cryptosystems, elliptic curve cryptography can provide better security and lower latency with shorter keys, rendering it more suitable for IoT security. This paper presents a high-efficiency and low-delay elliptic curve cryptographic architecture based on the NIST-$p_{256}$ prime field for IoT security applications. A modular square unit utilizes a fast partial Montgomery reduction algorithm, demanding just a mere four clock cycles to complete a modular square operation. The modular square unit can be computed simultaneously with the modular multiplication unit, consequently improving the speed of point multiplication operations. Synthesized on the Xilinx Virtex-7 FPGA platform, the proposed architecture completes one PM operation in 0.08 ms using 23.1 k LUTs at 105.3 MHz. These results show significantly better performance compared to that in previous works.

Turbo code is an error correction coding scheme close to the Shannon limit, usually used in wireless data transmission. Based on the parallel Turbo code algorithm, a parallel Turbo code circuit design scheme is proposed. In the encoder, the recursive systematic convolutional encoder is multiplexed. The decoder is divided into branch metric, recursive, maximum likelihood ratio, and external information calculation modules. The decoding algorithm is based on Max-Log-MAP, controlling the component decoder in parallel. And the state metric calculation in the decoding circuit is combined to reduce the overall power consumption effectively, enabling the encoder and decoder to be used in narrowband Internet of things (NB-IoT). Finally, the hardware scheme of the main functional modules of Turbo code encoding and decoding is designed and implemented. The results show that the dynamic power consumption is less than 50 mW. The overall on-chip power consumption is reduced by 40% at the frequency of 125 MHz compared with previous jobs.

Video-based action recognition, which needs to handle temporal motion and spatial cues simultaneously, remains a challenging task. In this paper, our motivation is to address this issue by fully utilizing temporal information. Specially, a novel light-weight Voting-based Temporal Correlation (VTC) module is proposed to enhance temporal information. Multiple branches with different temporal sampling intervals are included in this module and they are regarded as voters. The final classification result is “voted” by these branches together. VTC module integrates sparse temporal sampling strategy into feature sequences, so it mitigates the effect of redundant information and focuses more on temporal modeling. Additionally, we propose a simple and intuitive Similarity Loss (SL) to guide the training procedure of the VTC module and the backbone network. When we introduce confusion in the predicted vector intentionally, SL eases intra-class variation by discovering class-specific common motion patterns rather than sample-specific discriminative information. SL neither needs excessive parameter tuning during training nor adds significant computation overhead during test time. By combining VTC module and SL with complementary advances in the field, we clearly outperform state-of-the-art results and achieve 83.0, 98.4, 49.6 and 77.8 accuracy on HMDB51, UCF101, something-something-v1, and Kinetics respectively.

In this study, the authors focus on improving the spatio–temporal representation ability of three‐dimensional (3D) convolutional neural networks (CNNs) in the video domain. They observe two unfavourable issues: (i) the convolutional filters only dedicate to learning local representation along input channels. Also they treat channel‐wise features equally, without emphasising the important features; (ii) traditional global average pooling layer only captures first‐order statistics, ignoring finer detail features useful for classification. To mitigate these problems, they proposed two modules to boost 3D CNNs’ performance, which are temporal‐channel correlation (TCC) and bilinear pooling module. The TCC module can capture the information of inter‐channel correlations over the temporal domain. Moreover, the TCC module generates channel‐wise dependencies, which can adaptively re‐weight the channel‐wise features. Therefore, the network can focus on learning important features. With regards to the bilinear pooling module, it can capture more complex second‐order statistics in deep features and generate a second‐order classification vector. We can get more accurate classification results by combining the first‐order and second‐order classification vector. Extensive experiments show that adding our proposed modules to I3D network could consistently improve the performance and outperform the state‐of‐the‐art methods. The code and models are available at https://github.com/caijh33/I3D_TCC_Bilinear .

The deployment and application of large-scale Internet of Things require a large number of 13.56-MHz radio-frequency identification (RFID) reader chips with lower cost. The existing RFID reader module needs to integrate multiple chips, such as microcontroller and high-frequency (HF) RFID reader IC on a single printed circuit board (PCB), which has the bottleneck of cost, power consumption, stability, and reliability. In order to adapt to the development trend of high integration, miniaturization, and low-power consumption of RFID reader, this article proposes a fully integrated low-cost RFID reader System-on-a-Chip (SoC), which integrates RF transceiver and analog circuit, baseband protocol processing, microcontroller, memory, and interface circuit into a single chip. The proposed reader IC supports communication protocols, such as ISO/IEC 14443 Type A and Type B, ISO/IEC 15693, and ISO/IEC 7816. The reader can communicate with contact and contactless IC cards. The modulation depth of the transmitter circuit ranges from 1% to 100%, and the maximum transmitting current is 126 mA. The receiver circuit is composed of I/Q clock generation, switched capacitor sampling circuit, variable gain amplifier (VGA) with filter, comparator, and pulse shaping circuit, which has good anti-noise performance. This 13.56-MHz RFID reader SoC is fabricated in a 180-nm CMOS process and is housed in a 64-pin QFP package. The total area is 8.75 mm ² , including 1.47 mm ² for analog and RF circuits.

An NFC tag chip employing the ISO/IEC14443-A protocol is developed in SMIC 0.13 $\upmu$ m EEPROM 2P6M CMOS process, boasting a chip area of 620.03 $\upmu$ m $\times$ 567.93 $\upmu$ m and a power consumption of under 100 $\upmu$ W. The chip addresses critical issues such as reducing power consumption and minimizing area costs for covering numerous IoT nodes. For a small area of the chip, a specialized ESD protection circuit is proposed, efficiently multiplexing discharge transistors, cross-gate connected rectifiers, limiters for overvoltage protection, and load switch modulators within the chip’s limited space. For power efficiency, a compact 175.44 $\upmu$ m $\times$ 32.98 $\upmu$ m 18.52 $\upmu$ A LDO based on the current mirror and current feedback is presented for the DC supply during the 100% ASK modulation. Additionally, an ASK demodulator and a 13.56MHz $\pm$ kHz clock generator are designed in compact areas of 62.19 $\upmu$ m $\times$ 56.06 $\upmu$ m and 24.76 $\upmu$ m $\times$ 13.14 $\upmu$ m, respectively. These components ensure stable protocol communication with digital circuits and support a 7kb EEPROM, providing a comprehensive solution for NFC-based IoT information collection.