Neutrino oscillations are genuine quantum phenomena in which coherent oscillations are maintained over a long distance. As a result, in principle, the phenomena can be studied efficiently using quantum simulations. In today’s noisy quantum hardware, encoding neutrinos in a multiqubit system requires a redundant basis and tricky entangling gates. We encode a three-flavor neutrino in a superconducting qutrit and study its oscillations using Pontecorvo-Maki-Nakagawa-Sakata theory with time evolution expressed in terms of single qutrit gates. The qutrit is engineered from the multilevel structure of IBM transmon devices. High-fidelity gate control and readout are fine-tuned using programming microwave pulses using a high-level language. Our quantum simulations on real hardware match the analytical calculations well in three oscillation cases: vacuum, interaction with matter, and $CP$ violation.

This work applies concepts from algorithmic probability to Boolean and quantum combinatorial logic circuits. The relations among the statistical, algorithmic, computational, and circuit complexities of states are reviewed. Thereafter, the probability of states in the circuit model of computation is defined. Classical and quantum gate sets are compared to select some characteristic sets. The reachability and expressibility in a space-time-bounded setting for these gate sets are enumerated and visualized. These results are studied in terms of computational resources, universality, and quantum behavior. The article suggests how applications like geometric quantum machine learning, novel quantum algorithm synthesis, and quantum artificial general intelligence can benefit by studying circuit probabilities.

With the growth of quantum platforms for gate-based quantum computation, compilation holds a crucial role in deciding the success of the implementation. While there has been rich research in compilation techniques for the superconducting-qubit regime. The trapped-ion architectures, currently leading in robust quantum computations for their reliable operations, still lack competitive compilation strategies. This work introduces a unifying hardware abstraction, the “position graph”, representing various hardware architectures. With this abstraction, we model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures, enabling high-quality, scalable compilation methods. Specifically, we propose scheduling algorithms called SHuttling-Aware PERmutative (SHAPER) and SHuttling-AWare (SHAW) heuristic searches to tackle the complex constraints and dynamics of trapped-ion machines, with the cooperation of state-of-the-art permutation-aware mapping. These approaches generate executable circuits and native instructions that respect the physical constraints of shuttling-based architectures. We evaluate proposed algorithms across theorized and real architectures using the position graph framework. For completeness, we also introduce a linear program of trapped-ion scheduling that yields the optimal schedules, enabling a direct comparison with our heuristics. Our algorithm can successfully compile programs for extreme architectures where prior algorithms fail. When the baseline does complete, our produced schedules are 1.45 times faster on average, with best-case speedups up to 4 times faster.