3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.

Direct Cu-to-Cu bonding was achieved at temperatures of 150–250 °C using a compressive stress of 100 psi (0.69 MPa) held for 10–60 min at 10⁻³ torr. The key controlling parameter for direct bonding is rapid surface diffusion on (111) surface of Cu. Instead of using (111) oriented single crystal of Cu, oriented (111) texture of extremely high degree, exceeding 90%, was fabricated using the oriented nano-twin Cu. The bonded interface between two (111) surfaces forms a twist-type grain boundary. If the grain boundary has a low angle, it has a hexagonal network of screw dislocations. Such network image was obtained by plan-view transmission electron microscopy. A simple kinetic model of surface creep is presented; and the calculated and measured time of bonding is in reasonable agreement.

The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by transmission electron microscopy while the bond strength was examined from a diesaw test. Physical mechanisms explaining the different roles of postbonding anneals at temperatures above and below 300°C are discussed. A map summarizing these results provides a useful reference on process conditions suitable for actual microelectronics fabrication and three-dimensional integrated circuits based on Cu wafer bonding. © 2003 The Electrochemical Society. All rights reserved.