Under light load conditions, the phase-shifted full-bridge (PSFB) converter often has difficulty in realizing the zero-voltage switching (ZVS) of the lagging-leg by relying on the energy of its resonant inductor; however, for the series-parallel PSFB converter applied in high-power applications, the lagging-leg still has the problem of difficult realization of ZVS. Based on this, the paper analyzes the reasons why the series-parallel PSFB converter has difficulty in achieving ZVS for the lagging-leg under light and heavy loads. Under interleaved control, the ZVS of the lagging-leg over the full load range is realized by adding an auxiliary LC branch at the midpoint of the lagging-leg of both submodules. Based on the double-bridge input-parallel-output-series (IPOS) PSFB converter, analyzing the working principle of the circuit after adding the auxiliary LC branch and extending it to the series-parallel PSFB converter. The design requirements of the LC auxiliary branch of the dual-bridge series-parallel PSFB converter are given and the effects of the LC auxiliary branch on the module operating state and device stress are analyzed. On this basis, an extension is carried out to give the working principle and design method of the auxiliary LC branch of the N-bridge series-parallel PSFB converter. Finally, a 100 kW Matlab/Simulink simulation model verifies the superior performance of the proposed LC auxiliary branch to realize the lagging-leg ZVS of the series-parallel PSFB converter under light and heavy loads and achieves a 1.09% peak efficiency improvement at rated load.

Parasitic oscillations in the rectifier diode voltage of phase-shifted-full-bridge (PSFB) converters limit their application in high-voltage and high-power situations. The conventional analysis method for parasitic oscillation in rectifier diode voltage in PSFB converters treats the filter inductor as a constant current source and fails to consider the impact of changes in filter inductor current on the rectifier diode’s parasitic oscillation. Consequently, this approach does not apply when analyzing the rectifier diode voltage’s parasitic oscillations in high-power PSFB converters employing an input-parallel output-series (IPOS) configuration with interleaved drive. This research paper introduces an innovative equivalent circuit model for analyzing the parasitic oscillations of rectifier diode voltage in IPOS high-power PSFB converters. The model takes into account the mutual influence of rectifier diode voltage oscillations between submodules under interleaved control, considering the influence of changes in filter inductor current on rectifier diode parasitic oscillation. Based on the circuit model, we explain the mechanism of multiple oscillations of the rectifier diode voltage and the reason for the high peak of the first oscillation. Consequently, the interplay of rectifier diode voltage oscillations in IPOS high-power k-module PSFB converters under interleaved control is analyzed. To mitigate the adverse effects of rectifier diode voltage parasitic oscillation, a buffering strategy involving the connection of a resistor capacitor diode (RCD) circuit in parallel after the rectifier bridge is adopted, considering the structure of the IPOS high-power PSFB converter. The study provides a detailed analysis of the circuit’s operation mechanism upon incorporating the RCD buffer circuit and establishes the relationship between buffer capacitance, resistance, and spike voltage. Furthermore, a design method for buffer capacitors and discharge resistors in buffer circuits is presented. Finally, a 100 kW prototype is tested to verify the rectifier diode voltage oscillation mechanism of the IPOS high-power PSFB converter and the rationality of the buffer capacitor and discharge resistor design method under the interleaved drive approach.