With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

In this work, we present an asynchronous MTJ-CMOS hybrid system with extremely fine-grained voltage scaling (EFGVS) technique. The supply voltage of the system is turned on/off by asynchronous bundled-data handshake signals. The MTJ write circuit is variation robust, self-terminated and redundant-write preventing. Besides, EFGVS and asynchronous data driven handshake enhance the timing robustness by removing the matching delay elements and reducing timing assumptions. The completion detection circuitry is also simplified. A RISC processor with proposed techniques is designed and fabricated by 55nm technology. The voltage supplies are turned on/off within tens of picoseconds. The energy for writing MTJs is 0.45pJ. The tolerance of the minimum TMR due to process variation is 75%. Sleep mode leakage power can be reduced over 10× by powering off modules with the Break-even Time of 23.6 ns. Because of the extremely fine-grained voltage scaling, no more than 20% of the modules are powered on during the execution.