With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

With the development of Very Large-Scale Integration (VLSI) technology, circuit designers are increasingly focused on achieving low power, high speed, and small area. Among various circuit components, multiplier circuits play an important role in improving the overall system performance due to their significant power consumption and impact on circuit speed. In this paper, we propose a novel 8-bit signed multiplier based on the Pass Transistor Logic (PTL) that outperforms existing designs. The post-layout simulation results show that the proposed design reduces area, delay, and power by 13.45%, 9.72%, and 15.19%, respectively, compared to the multiplier synthesized using Synopsys Design Compiler (DC). Compared to other 8-bit multipliers proposed in references, our design also shows at least a 27.66% improvement in power-delay product (PDP). Additionally, the proposed circuits exhibit superior performance at different operating voltages and process corners.

The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.