Junction temperature is an important converter design/operation parameter as well as a significant indicator of device health condition. As compared to the Si counterparts, it is more critical for SiC devices due to the reliability concern introduced by immaturity of new material and packaging. This paper proposes a practical implementation using an intelligent gate drive for online junction temperature monitoring of SiC devices based on turn-off delay time as the thermo-sensitive electrical parameter. First, the sensitivity of turn-off delay time on the junction temperature for fast switching SiC devices is analyzed. A gate impedance regulation assist circuit is proposed to enhance the sensitivity by a factor of 60 in the case study with little penalty of the power conversion performance. Next, an online monitoring unit based on gate assist circuits is developed to monitor the turn-off delay time in real time with the resolution within hundreds of ps. As a result, the micro-controller is capable of “reading” junction temperature during the converter operation. Finally, a SiC-based half-bridge inverter is constructed with the intelligent gate drive consisting of the gate impedance regulation circuit and online turn-off delay time monitoring unit. Experimental results demonstrate the feasibility and accuracy of the proposed approach.

To better support the superconducting propulsion system in the future aircraft applications, the technologies of high-power high switching frequency power electronics systems at cryogenic temperatures should be investigated. This article presents the development of a 40-kW cryogenically cooled three-level active neutral point clamped inverter with 3 kHz output line frequency and 140 kHz switching frequency. Si mosfets are characterized at cryogenic temperatures, and the results show that they have promising performance such as lower on-resistance and switching loss. The design of the inverter is presented in detail with the special consideration of the cryogenic temperature operation. Moreover, a packaging and integration architecture is designed and fabricated to demonstrate the feasibility and performance of the inverter in the lab. It is able to achieve no leakage with good thermal and air insulation. With the inverter and packaging, the experimental results show that the inverter operates properly at cryogenic temperatures. The loss is measured at different load conditions, and the loss analysis is given, which shows that the cryogenically cooled inverter has 30% less loss than operating at room temperature.

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di / dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di / dt and dv / dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

Paralleling three phase three-level inverters is gaining popularity in industrial applications. However, analytical models for the harmonics calculation of a three-level neutral point clamped (NPC) inverter with popular space vector modulation (SVM) are not found in the literature. Moreover, how interleaving angle impacts the dc- and ac-side harmonics and electromagnetic interference (EMI) harmonics in parallel interleaved three-level inverters and how to optimize interleaving angle to reduce these harmonics have not been discussed in the literature. Furthering previous study, this article presents the modeling, analysis, and reduction of harmonics in paralleled and interleaved three-level NPC inverters with SVM. Analytical models for harmonic calculation are developed, and the dc-side harmonics characteristics of an NPC inverter are identified. The impact of interleaving angle on the ac-side voltage and dc-link current harmonics of parallel interleaved three-level NPC inverters is comprehensively studied. The impact of switching frequency and interleaving angle on EMI harmonics is also illustrated. Optimal interleaving angle ranges to reduce these harmonics are derived analytically. The developed models and harmonic reduction analysis are verified experimentally with two paralleled and interleaved three-level NPC inverters.

This article establishes an analytical model for the device drain-source overvoltage related to the two loops in three-level active neutral point clamped (3L-ANPC) converters. Taking into account the nonlinear device output capacitance, two common modulation methods are investigated in detail. The results show that the line switching frequency device usually has higher overvoltage, and the switching speed of the high switching frequency device is not strongly influenced by the multiple loops. By keeping the nonactive clamping switch off, the effect of the nonlinear device output capacitance can be significantly mitigated, which helps reduce the overvoltage. Moreover, the loop inductance can be reduced with vertical loop layout and magnetic cancellation in the printed circuit board and busbar design. A 500-kVA 3L-ANPC converter using silicon carbide mosfets was built and tested. The experimental results validate the overvoltage model of the two modulation methods as well as the busbar design. With the nonactive clamping switch off, the overvoltage of both the high and line switching frequency devices is significantly reduced, which helps achieve higher switching speed.