Sahil Shah

Dr. Sahil Shah


Research Focus & Metrics

Academic Career Length

24Years (2003-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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9 September 2022 in Nature Communications
Verified
Journal Article
Open access
PDF file
HYHaitao Yang
Haitao Yang
JLJiali Li
Jiali Li
XXXiao Xiao
Xiao Xiao
JWJiahao Wang
Jiahao Wang
YLYufei Li
Yufei Li
PCPo-Yen Chen
Po-Yen Chen
Wearable strain sensors that detect joint/muscle strain changes become prevalent at human–machine interfaces for full-body motion monitoring. However, most wearable devices cannot offer customizable opportunities to match the sensor characteristics with specific deformation ranges of joints/muscles, resulting in suboptimal performance. Adequate wearable strain sensor design is highly required to achieve user-designated working windows without sacrificing high sensitivity, accompanied with real-time data processing. Herein, wearable Ti3C2Tx MXene sensor modules are fabricated with in-sensor machine learning (ML) models, either functioning via wireless streaming or edge computing, for full-body motion classifications and avatar reconstruction. Through topographic design on piezoresistive nanolayers, the wearable strain sensor modules exhibited ultrahigh sensitivities within the working windows that meet all joint deformation ranges. By integrating the wearable sensors with a ML chip, an edge sensor module is fabricated, enabling in-sensor reconstruction of high-precision avatar animations that mimic continuous full-body motions with an average avatar determination error of 3.5 cm, without additional computing devices.

1 October 2025 in npj Unconventional Computing
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Journal Article
Open access
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YBYongmin Baek
Yongmin Baek
BBByungjoon Bae
Byungjoon Bae
HSHyojin Shin
Hyojin Shin
CSCharana Sonnadara
Charana Sonnadara
HCHaein Cho
Haein Cho
KLKyusang Lee
Kyusang Lee
Artificial intelligence technology transforms traditional sensors from passive data collectors into active computing nodes, performing data processing at the edge. This paradigm shift toward in- and near-sensor computing mitigates inherent inefficiencies associated with data traversal between sensing, memory, and processing units. We introduce emerging device technologies, circuit architectures, algorithmic frameworks, and applications implementing artificial intelligence of things. Our perspective presents technical capabilities, implementation challenges, and strategic roadmaps for edge intelligence.

6 July 2017 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
SKSihwan Kim
Sihwan Kim
SSSahil Shah
Sahil Shah
JHJennifer Hasler
Jennifer Hasler
We present a calibration flow for a large-scale floating-gate (FG) system-on-chip field programmable analog array. We focus on characterizing the FG programming infrastructure and hot-electron injection parameters, MOSFET parameters using the EKV model, and calibrating digital-analog converters and analog-digital converters. In addition, threshold voltage mismatches on FG devices due to their indirect structure are characterized using on-chip measurement techniques. The calibration results in enabling a digital approach, where a design can be programmed without having to deal with the local and global mismatches, on a reconfigurable analog system. This paper shows the results of a compiled nonlinear classifier block comprising a vector-matrix-multiplier and a winner-takes-all on three different calibrated chips.

15 February 2017 in IEEE Transactions on Circuits and Systems I: Regular Papers
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Journal Article
Closed access
SSSahil Shah
Sahil Shah
JHJennifer Hasler
Jennifer Hasler
This paper presents a low-power built-in self-test system to compensate for mismatch and variations in CMOS IC. The system is designed and compiled on a low-power field programmable analog array (FPAA) fabricated on a 350-nm CMOS process. A second-order bandpass filter is used as a device under test. A set of 12 parallel filter banks are compiled on three different FPAA chips and compensated for local mismatch and variations in the bias current, and mismatch in parasitic and routing capacitances. The bandpass filters are biased in subthreshold regime and the system of 12 parallel filter banks consumes a power of $7.072~\mu \text{W}$ . The proposed tuning algorithm reduces variation in center frequency to 5.07% compared with a variation of 10.16% when they are not tuned, variation in quality factor to 8.52% from 13.86%, and variation in the gain at the center frequency to 3.83% from 21.04%. These values are deviation of the parameters from its mean for the data taken from three different FPAA chips fabricated on the same wafer.

24 November 2017 in IEEE Journal on Emerging and Selected Topics in Circuits and Systems
Verified
Journal Article
Closed access
SSSahil Shah
Sahil Shah
JHJennifer Hasler
Jennifer Hasler
This paper focuses on the circuit aspects required for an on-chip, on-line SoC large-scale Field Programmable Analog Array (FPAA) learning for Vector-Matrix Multiplier (VMM) + Winner-Take-All (WTA) classifier structure. We start by describing the VMM+WTA classifier structure, and then show techniques required to handle device mismatch. The approach is initially explained using a VMM+WTA as a two-input XOR classifier structure. The approach requires considering the entire mixed-mode system, including the analog classifier data path, control circuitry for weight updates, and digital algorithm for computing digital weight updates and resulting FG programming during the algorithm.

1 December 2023 in Journal of Neural Engineering
Verified
Journal Article
Open access
PDF file
ETElijah A Taeckens
Elijah A Taeckens
SSSahil Shah
Sahil Shah
Objective. Spiking neural networks (SNNs) are powerful tools that are well suited for brain machine interfaces (BMI) due to their similarity to biological neural systems and computational efficiency. They have shown comparable accuracy to state-of-the-art methods, but current training methods require large amounts of memory, and they cannot be trained on a continuous input stream without pausing periodically to perform backpropagation. An ideal BMI should be capable training continuously without interruption to minimize disruption to the user and adapt to changing neural environments. Approach. We propose a continuous SNN weight update algorithm that can be trained to perform regression learning with no need for storing past spiking events in memory. As a result, the amount of memory needed for training is constant regardless of the input duration. We evaluate the accuracy of the network on recordings of neural data taken from the premotor cortex of a primate performing reaching tasks. Additionally, we evaluate the SNN in a simulated closed loop environment and observe its ability to adapt to sudden changes in the input neural structure. Main results. The continuous learning SNN achieves the same peak correlation ( ρ = 0.7 ) as existing SNN training methods when trained offline on real neural data while reducing the total memory usage by 92%. Additionally, it matches state-of-the-art accuracy in a closed loop environment, demonstrates adaptability when subjected to multiple types of neural input disruptions, and is capable of being trained online without any prior offline training. Significance. This work presents a neural decoding algorithm that can be trained rapidly in a closed loop setting. The algorithm increases the speed of acclimating a new user to the system and also can adapt to sudden changes in neural behavior with minimal disruption to the user.