We presented an explicit empirical model of the thermal resistance of AlGaN/GaN high-electron-mobility transistors on three distinct substrates, including sapphire, SiC, and Si. This model considered both a linear and non-linear thermal resistance model of AlGaN/GaN HEMT, the thickness of the host substrate layers, and the gate length and width. The non-linear nature of channel temperature—visible at the high-power dissipation stage—along with linear dependency, was constructed within a single equation. Comparisons with the channel temperature measurement procedure (DC) and charge-control-based device modeling were performed to verify the model’s validity, and the results were in favorable agreement with the observed model data, with only a 1.5% error rate compared to the measurement data. An agile expression for the channel temperature is also important for designing power devices and monolithic microwave integrated circuits. The suggested approach provides several techniques for investigation that could otherwise be impractical or unattainable when utilizing time-consuming numerical simulations.

Frequency dispersion in the accumulation region seen in multifrequency capacitance–voltage characterization, which is believed to be caused mainly by border traps, is a concerning issue in present-day devices. Because these traps are a fundamental property of oxides, their formation is expected to be affected to some extent by the parameters of oxide growth caused by atomic layer deposition (ALD). In this study, the effects of variation in two ALD conditions, deposition temperature and purge time, on the formation of near-interfacial oxide traps in the Al₂O₃ dielectric are examined. In addition to the evaluation of these border traps, the most commonly examined electrical traps—i.e., interface traps—are also investigated along with the hysteresis, permittivity, reliability, and leakage current. The results reveal that a higher deposition temperature helps to minimize the formation of border traps and suppress leakage current but adversely affects the oxide/semiconductor interface and the permittivity of the deposited film. In contrast, a longer purge time provides a high-quality atomic-layer-deposited film which has fewer electrical traps and reasonable values of permittivity and breakdown voltage. These findings indicate that a moderate ALD temperature along with a sufficiently long purge time will provide an oxide film with fewer electrical traps, a reasonable permittivity, and a low leakage current.

Our investigation focused on assessing the influence of the metamorphic buffer in metamorphic high-electron-mobility transistors (MHEMT) that were grown on GaAs substrates. While an MHEMT exhibited elevated off-state current levels, its direct current (DC) and radio frequency (RF) traits were found to be comparable to those of InP-based lattice-matched high-electron-mobility transistors (LM-HEMTs). However, the Pulsed I–V measurement results confirmed the presence of the fast transient charging effect, leading to a more substantial degradation in drain current observed in MHEMT. In addition, through the low-frequency noise characteristics, it was confirmed that the dominant trapping location was located in the bulk site. The slope of the 1/f noise measurement indicated that the primary trapping site was in proximity to the bulk traps. The carrier-number-fluctuation (CNF) model was employed to extract the bulk trap density (N_t). For the LM-HEMTs, the value was at 3.27 × 10¹⁶ eV⁻¹·cm⁻³, while for the MHEMT, it was 3.56 × 10¹⁷ eV⁻¹·cm⁻³.