A low-cost embedded system for high-energy radiation detection applications was developed for national security proposes, mainly to detect nuclear material and send the detection event to the cloud in real time with tracking capabilities. The proof of concept was built with state-of-the-art electronics such as an adequate Si-based photodetector, a trans-impedance amplifier, an ARM Cortex M4 microcontroller with sufficient ADC capture capabilities, an ESP8266 Internet of Things (IoT) module, an optimized Message Queuing Telemetry Transport (MQTT) protocol, a MySQL data base, and a Python handler program. The system is able to detect alfa particles and send the nuclear detection events to the CloudMQTT servers. Moreover, the detection message records the date and time of the ionization event for the tracking application, and due to a particular MQTT-optimized protocol the message is sent with low latency. Furthermore, the designed system was validated with a standard radiation instrumentation preamplifier 109A system from ORTEC company, and more than one node was demonstrated with an internet connection employing a 20,000 bits/s CloudMQTT plan. Therefore, the design can be escalated to produce a robust big data multisensor network.

This work presents the design of a microprocessor synthesized in FPGA based on the IEC 61131-3 standard. We report the architecture, and the operation of the internal hardware which allows the execution of Instruction List (IL). One of the most important components is the operands_selector block which allows memory elements, inputs, or outputs of the microprocessor to be treated as operands. Two ALUs are available to perform a bit, integer, and floating-point operations. The implementation of this microprocessor allows concluding that our designed microprocessor implemented in xc7a100tcsg324 (Xilinx) or EP4CE10E22C8 (Intel) FPGAs is superior in their execution times compared to the microprocessor evaluated in early studies and to one of the S7-1500 family processor.

This study presents the design and implementation of a PLC microprocessor adhering to the IEC-61131-3 standard, executed on a Cyclone-V FPGA using a DE10-NANO development board. Our microprocessor optimizes the central processing unit by streamlining the data path, achieving a remarkable simulated response time of approximately 60 ns, equivalent to three clock cycles at a 50MHz frequency for Boolean operations. To substantiate our approach, we conducted practical experiments utilizing a FESTO conveyor station, employing relays as actuators, and incorporating optical and inductive sensors. The results underscore the feasibility of our proposed approach and serve as practical validation of its efficacy. This work introduces a promising avenue for the development of cost-effective PLCs employing SoC FPGA variants. Additionally, a thorough comparison of execution times with other early reported architectures. Our microprocessor outperforms even well-established PLCs like the S7-312, with substantial reductions in execution times of 94.54% for floating-point operations, 71.42% to 93.33% for word operations, and up to 78.57% for bit operations.