Single event burnout (SEB) of enhancement mode GaN high-electron mobility transistors (HEMTs) under heavy ion irradiation is systematically studied based on simulations in this work. Susceptibility to SEB of different particle incidence environments is investigated to determine the device's sensitive position. Under these conditions, the mechanism of SEB in enhancement mode HEMTs is mainly associated with the charge congestion and subsequent continuous impact ionization. A hardened HEMT structure with the gate and drain double field plates is proposed correspondingly. Apart from better output characteristics and almost 25% improvement of breakdown voltage, the hardened structure also demonstrates better tolerance of SEB. This hardened structure can modify the electric field in the high field region so that charge accumulation is reduced significantly, thus effectively decreasing the possibility of SEB's occurrence. With a vertical heavy ion strike of 63.8 MeV ·cm ² /mg linear energy transfer (LET), SEB threshold voltage of the conventional structure HEMT is 160 V, while that of the hardened structure HEMT is much higher, reaching 249 V. Besides, the hardened device exhibits better SEB tolerance than the conventional device even at different higher LET conditions. Furthermore, the contribution to SEB tolerance of each field plate is also discussed.

In recent years, 3-D GaN-based transistors have been intensively studied for their dramatically improved performance. However, thermal analysis of such devices is often oversimplified using the conventional Fourier's law in thermal simulations. In this aspect, accurate temperature predictions can be achieved by coupled phonon and electron Monte Carlo (MC) simulations that track the movement and scattering of individual phonons and electrons. Based on these MC simulations for the transistor region and the Fourier's law analysis for the rest of the chip, accurate electrothermal simulations are carried out on a nanowire-based GaN transistor to reveal the temperature rise in such devices.

Silicon carbide MOSFET has been commercialized for many years. Its performance is still improving especially for high-frequency application. High-frequency figure-of-merit (HF-FOM) RON* CGD and RON* QGD were used for a comprehensive evaluation of the performance of MOSFET. In this article, SiC planar MOSFETs with different p-body designs were comparatively studied. A new planar MOSFET with buffered gate and thick central oxide gate structure (TCOX-MOS) was proposed to further improve the gate oxide electric field in OFF-state and HF-FOM. Compare to the conventional planar MOSFET (C-MOS), the maximum gate oxide electric field, gate-drain charge, and HF-FOM (RON * QGD) of TCOX-MOS are 32%, 83%, and 84% lower, respectively. Furthermore, TCOX-MOS shows less short-channel effects by better channel shielding structure. The results show that TCOX-MOS is a more attractive device structure.

AlGaN/GaN high electron mobility transistors (HEMTs) grown on Fe-modulation-doped (MD) and unintentionally doped (UID) GaN buffer layers are investigated and compared. Highly resistive GaN buffers (10⁹ Ωcm) are induced by individual mechanisms for the electron traps' formation: the Fe MD buffer (sample A) and the UID buffer with high density of edge-type dislocations (7.24 × 10⁹ cm⁻², sample B). The 300 K Hall test indicates that the mobility of sample A with Fe doping (2503 cm²V⁻¹s⁻¹) is much higher than sample B (1926 cm²V⁻¹s⁻¹) due to the decreased scattering effect on the two-dimensional electron gas. HEMT devices are fabricated on the two samples and pulsed I–V measurements are conducted. Device A shows better gate pinch-off characteristics and a higher threshold voltage (−2.63 V) compared with device B (−3.71 V). Lower gate leakage current |I _GS | of device A (3.32 × 10⁻⁷ A) is present compared with that of device B (8.29 × 10⁻⁷ A). When the off-state quiescent points Q₂ (V _GQ2 = −8 V, V _DQ2 = 0 V) are on, V _th hardly shifts for device A while device B shows +0.21 V positive threshold voltage shift, resulting from the existence of electron traps associated with the dislocations in the UID-GaN buffer layer under the gate. Under pulsed I–V and transconductance G _m −V _GS measurement, the device with the Fe MD-doped buffer shows more potential in improving reliability upon off-state stress.