The consumer electronics markets have increased the demand for high‐speed and low‐power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel‐prefix adders, exhibit high‐power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade‐off between the delay and power‐consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel‐prefix adders the least‐significant carries are produced much sooner than the most‐significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least‐significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least‐significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65‐nm‐TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area‐delay‐product in comparison with state‐of‐the‐art wide‐operand adders.

Residue number systems (RNSs) are efficient alternatives to positional number systems, providing fast and power-efficient computational systems. The key feature of the RNS benefitting modern embedded systems and the Internet-of-Thing (IoT) edge devices is its energy efficiency. Modular addition is the most important and frequent operation applied on the components of RNS, including arithmetic units in the channels as well as forward and reverse converters. The small and medium dynamic range requirements of low-power embedded and edge devices make the usage of the thermometer coding (TC) and one-hot coding (OHC) viable, reducing the power consumption and improving the energy efficiency of modulo addition in comparison to regular binary representations. Based on these techniques, this paper presents two new energy-efficient modular adders, which, due to the carry-free internal computations, are also highly performing. The proposed modular adders based on the TC and OHC result in average improvements of 38% and 34.5% for the delay, 27% and 14.5% for the circuit area, 29.5% and 6.3% for energy consumption, and about 54.9% and 44.2% for the area-delay product (ADP), respectively, in comparison with the related state of the art.

The design of inexact circuits at the transistor level remarkably improves figures of merits such as power consumption, delay, energy, and area. Therefore, inexact technique for designing circuits has attracted the attention of researchers worldwide. Designing inexact Full Adder cell as a building block of a variety of arithmetic circuits can affect the entire electronic system’s performance. In this paper, two novel inexact 1-bit Full Adder cells are presented using carbon nanotube field effect transistors (CNFETs). The capacitive threshold logic (CTL) is used to realize the proposed cells. Comprehensive simulations at two levels of abstraction, i.e., application and hardware are carried out to evaluate the efficacy of these circuits. First, the motion detector which is one of the image processing applications is deployed in MATLAB software to measure peak signal-to-noise ratio (PSNR) figure of merit. At hardware level, the HSPICE tool is used to carry out simulations and measure power, delay, power-delay product (PDP), energy-delay product (EDP), power-delay-area product (PDAP) and power-delay-area-PSNR product (PDAPP). Simulation results confirmed the superiority of the proposed Full Adder cells compared to others. For instance, the proposed 6TIFA improves PDAPP metric at least 21% and at most 76% compared to its counterparts at 0.9V power supply.

As circuit complexity grows, designers are exploring ternary logic as an alternative to binary logic to solve interconnection and energy problems. One effective approach to implementing ternary logic-based circuits is to use a multiple-threshold voltage (multi- V _th ) design. In particular, graphene nanoribbon (GNR)-based field-effect transistors (GNRFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology for sub-32 nm feature sizes, as GNRs have excellent properties that can overcome scaling issues in CMOS. This paper introduces a ternary multiplier implemented with 32 nm GNRFET technology, which demonstrates high efficiency with only 26 transistors. Simulation results show that the proposed multiplier improves power dissipation and product-delay-power (PDP) by at least 37.30% and 22.22%, respectively, compared to existing multiplier designs when run at 0.9 V. Moreover, our proposed design is implemented with a carbon nanotube-based FET (CNTFET) technology. The GNRFET-based multiplier improved power and PDP by 41.77% and 30%, respectively in the cost of increasing the delay by 25%, compared to its CNTFET-based equivalent. Finally, we analyze the proposed multiplier under the process and environmental parameters variations of GNRFET technology. Overall, our results demonstrate the advantages of using GNRFET technology for implementing ternary logic-based circuits and provide insight into the impact of different design choices on performance.

Cognitive Radio Ad-hoc Network (CRAHN) is one of the building blocks of heterogeneous networks to improve accessibility and spectral efficiency. The prioritized spectrum access is the key to maintain the efficiency of CRAHN. However, in CRAHN, TCP results in severe throughput reduction since it cannot differentiate between the packet loss due to SU’s transmission-blocking and packet loss due to congestion. In this paper, two significant events are investigated that caused secondary user blocking. Besides, using a Continuous-Time Markov chain (CTMC), we develop an analytical model to estimate the TCP throughput and end to end delay. The experimental results based on the NS2 confirm the accuracy of the proposed model and show that the throughput and the average end-to-end delay are improved based on the proposed CTMC model comparing with some transport protocol in the cognitive radio networks. The performance results through simulation show that the proposed model not only provides less energy consumption, also achieves up to 40% and 20% improvement of the throughput comparing with the classical TFRC and TFRC-CR, respectively.