Residue Number System (RNS) is a non-weighted number system which was proposed by Garner back in 1959 to achieve fast implementation of addition, subtraction and multiplication operations in special-purpose computations. Unfortunately, RNS did not turn out as a popular alternative to two?s complement number system in those days. The rigidity of instruction set architectures of the market-dominant computers and microprocessors then has been the main barrier to sustain the development of RNS-based applications. In recent years, technological advancement in semiconductor technology has revived the interests to reconsider RNS for application-specific computing. There are at least two unique motivations which make RNS computations more attractive and applicable in modern digital signal processing applications. Firstly, the modular and distributive properties of RNS are used to achieve performance improvements especially in the emerging distributed and ubiquitous computing platforms such as cloud, wireless ad hoc networks, and applications which require tolerance against soft error. Secondly, energy efficiency becomes a key driver in the continual densification of complementary metal oxide semiconductor (CMOS) digital integrated circuits. The high degree of computational parallelism in RNS offers new degree of freedom to optimize energy performance, particularly for very long word length arithmetic such as those involved in the hardware implementation of cryptographic algorithms. Our aim in this paper is to show this revolution by discussing interesting development in RNS and foster the innovative use of RNS for more applications. Different applications of RNS are investigated to demonstrate how this unconventional number system can be leveraged to benefit their implementation.

In this paper, we introduce two new 4-moduli sets {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹-1} and {2ⁿ-1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1} for developing efficient large dynamic range (DR) residue number systems (RNS). These moduli sets consist of simple and well-formed moduli which can result in efficient implementation of the reverse converter as well as internal RNS arithmetic circuits. The moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹-1} has 5n-bit DR and it can result in a fast RNS arithmetic unit, while the 6n-bit DR moduli set {2ⁿ-1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1} is a conversion friendly moduli set which can lead to a high-speed and low-cost reverse converter design. Next, efficient reverse converters for the proposed moduli sets based on new Chinese remainder theorems (New CRTs) are presented. The converter for the moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2²ⁿ⁺¹-1} is derived by New CRT-II with better performance compared to the reverse converter for the latest introduced 5 n-bit DR moduli set {2ⁿ-1, 2ⁿ, 2ⁿ+1, 2^n-1-1, 2ⁿ⁺¹-1}. Also, New CRT-I is used to achieve a high-performance reverse converter for the moduli set {2ⁿ-1, 2ⁿ+1, 2²ⁿ, 2²ⁿ+1}. This converter has less conversion delay and lower hardware requirements than the reverse converter for a recently suggested 6n-bit DR moduli set {2ⁿ-1, 2ⁿ+1, 2²ⁿ-2, 2²ⁿ⁺¹-3} .

The residue number system (RNS) has been an important research field in computer arithmetic for many decades, mainly because of its carry-free nature, which can provide high-performance computing architectures with superior delay specifications. Recently, research on RNS has found new directions that have resulted in the introduction of efficient algorithms and hardware implementations for RNS with much better performance than previous ones. Furthermore, the applicability of RNS in many computer and digital signal processing (DSP) applications has simultaneously greatly increased. Hence, the need is evident for the development of a new and well-organized RNS teaching method with emphasis on recent achievements. In this paper, a step-by-step teaching process for RNS that describes RNS design in separate parts is presented. Each part is investigated in detail, taking into account the recent research performed on RNS. The compatibility of the proposed method with the new RNS research trends makes this method suitable for researchers as well as students.

The residue number system (RNS) is an unconventional number system which can lead to parallel and fault-tolerant arithmetic operations. However, the complexity of residue-to-binary conversion for large number of moduli reduces the overall RNS performance, and makes it inefficient for nowadays high-performance computation systems. In this paper, we present an improved approximate Chinese remainder theorem (CRT) with the aim of performing efficient residue-to-binary conversion for general RNS moduli sets. To achieve this aim, the required number of fraction bits for accurate residue-to-binary conversion is derived. Besides, a method is proposed to substitute fractional calculations by similar computations based on integer numbers to have a hardware amenable algorithm. The proposed approach results in high-speed and low-area residue-to-binary converters for general RNS moduli sets. Therefore, with this conversion method, high dynamic range residue number systems suitable for cryptography and digital signal processing can be designed.

Convolutional neural networks (CNNs) are used in our daily life, including self-driving cars, virtual assistants, social network services, healthcare services, and face recognition, among others. However, deep CNNs demand substantial compute resources during training and inference. The machine learning community has mainly focused on model-level optimizations such as architectural compression of CNNs, whereas the system community has focused on implementation-level optimization. In between, various arithmetic-level optimization techniques have been proposed in the arithmetic community. This article provides a survey on resource-efficient CNN techniques in terms of model-, arithmetic-, and implementation-level techniques, and identifies the research gaps for resource-efficient CNN techniques across the three different level techniques. Our survey clarifies the influence from higher- to lower-level techniques based on our resource efficiency metric definition and discusses the future trend for resource-efficient CNN research.

The consumer electronics markets have increased the demand for high‐speed and low‐power adders with large operands to be integrated in modern portable systems. Traditional fast adder architectures, such as parallel‐prefix adders, exhibit high‐power consumption for large operands. The hybrid design is one of the most promising techniques to achieve a trade‐off between the delay and power‐consumption for the addition of large operands. This study presents a new hybrid adder architecture, specifically designed for large operands, based on the premise that in large parallel‐prefix adders the least‐significant carries are produced much sooner than the most‐significant ones. Therefore, the authors avoid the incorporation of fast architectures related with the application of carries to the final summation least‐significant bits, with no impact on the critical path. This leads to a reduction in the area of the summation blocks in the least‐significant positions without compromising the speed. Moreover, the complement of the carries is generated and propagated inside the carry network of the proposed adder in order to decrease the delay. VLSI implementation results on the 65‐nm‐TSMC technology show that the proposed adder achieves >25% of energy savings, and a reduction of over 30% of the area‐delay‐product in comparison with state‐of‐the‐art wide‐operand adders.