The complexity of vehicle applications and the need of reducing the number of processing units are giving great audience to system virtualization. Virtualized architectures with diverse Automotive Safety Integrity Level (ASIL) in the same multicore hardware, known as Mixed Criticality Systems (MCSs), offer flexibility but are extremely challenging in terms of timing validation and resources partitioning. At the same time, RISC- V technologies are becoming central in automotive thanks to open source licensing and customizable solutions. However, most of these architectures cannot sustain MCSs for the absence of features that can be performed only through hardware extensions. In this paper we define details and show a preliminary design and synthesis of a Programmable PMU (PPMU). In virtual systems an extension reporting hardware performance is essential to absolve timing analysis and shared resources balancing purposes. Moreover, in the paper we present a table containing major Hardware Events (HEs) we are interested in, and that can be monitored. The HEs are classified by the role they have in a MCS: Functional Safety (FuSa) analysis or Performance analysis. The synthesis of the PPMU highlighted that the device introduces a limited hardware overhead, e.g. in the worst case the unit uses less than 3 % of available programmable logic of a xczu9eg FPGA device.

The current main trends of the automotive industry, namely Automation, Connection, and Electrification, place novel challenges in products development. In particular, the Industry needs to increase the computational power availability in vehicles, trying to keep the same costs as in the past. Of course, since automotive applications can affect people’s safety, there is also the need to keep the same reliability levels. All of this has to be reached with fewer hardware components to limit costs. Another advantage is that, considering the usage of Commercial-Off-The-Shelf chiplets featuring multiple core with diverse levels of integrities, it allows to use the lower-integrity ones increasing the overall computation capabilities for a given component. This paper proposes a novel approach based on Software-Implemented Hardware Fault Tolerance, such as Control Flow Checking and Data Hardening, to move forward in this direction, addressing mixed-criticality multi-core systems. The main focus is exploiting the computational power of lower-integrity cores or hardware accelerators to execute safety-critical tasks without increasing the risk level.

In this manuscript, we propose a configurable hardware device in order to build a coherent data log unit. We address the need for analyzing mixed-criticality systems, thus guaranteeing the best performances without introducing additional sources of interference. Log data are essential to inspect the behavior of running applications when safety analyses or worst-case execution time measurements are performed. Furthermore, performance and timing investigations are useful for solving scheduling issues to balance resource budgets and investigate misbehavior and failure causes. We additionally present a performance evaluation and log capabilities by means of simulations on a RISC-V use case. The simulations highlight that such a data log unit can trace the execution from a single- to an octa-core microcontroller. Such an analysis allows a silicon developer to obtain the right sizings and timings of devices during the development phase. Finally, we present an analysis of a real RISC-V implementation for a Xilinx UltraScale+ FPGA, which was obtained with Vivado 2018. The results show that our data log unit implementation does not introduce a significant area overhead if compared to the RISC-V core targeted for tests, and that the timing constraints are not violated.