This article presents the design of an LC -Tank voltage-controlled oscillator (VCO) for space and high-energy physics (HEP) applications. The main goal of this work is to design a radiation-hard oscillator to be integrated into a phase-locked loop (PLL), compliant with (but not limited to) SpaceFibre protocol requirements, which is able to support the 6.25 GHz frequency. The full custom schematic and layout of the LC -VCO are reported in this work. The LC -VCO is implemented in a commercial 65 nm CMOS technology, and its electrical characterization highlights a tuning range (TR) from 5.4 to 6.8 GHz. An experimental chip was fabricated and irradiated with X-rays up to 1 Grad (SiO ₂ ) total ionizing dose (TID) level at CERN facility. The TID experiment and measurement results are analyzed and discussed. The LC -VCO shows a frequency degradation of 2.54% and a 3.34% increment in phase noise at 1 Grad TID. The results achieved are of interest for both space and HEP applications.

This paper presents the design and experimental verification of two drivers designed to be compliant with the high radiation dose levels present in the inner layers of the CERN's Large Hadron Collider (LHC) experimental chambers. The drivers, designed to face up to 800 Mrad (SiO ₂ ) Total Ionizing Dose, are able to sustain up to 5 Gbps bit-rate links when integrated in a 65 nm CMOS technology. They are designed to drive two Silicon Photonics optical modulators, Mach Zehnder Modulator and Ring Resonator, which have shown high rad-tolerant levels. The high dose level hardness of the drivers has been achieved by adopting the following Radiation Hardening By Design (RHBD) techniques: enhancement of the MOSFETs model to take into account the effects of high radiation dose levels and of single event effects on the devices, avoidance of using P-MOSFETs, increase of the minimum MOSFET lengths for the switching devices, and the use of Enclosed Layout Transistors shape plus some layout precautions. Moreover, to increase the drivers speed, techniques like buffer chain and inductive peaking are used in the drivers' design. The experimental results have verified the matching of the high-speed high-voltage constraint required by the application. The Total Ionization Dose tests have shown, at 800 Mrad (SiO ₂ ), a 30% and 25% amplitude reduction of the output signals eye diagrams of the Mach Zehnder Modulator driver and of the Ring Resonator driver, respectively. In the worst case, in which the drivers will be placed within 5 cm from the beamline of the CMS experiment of the upgraded LHC, the heavy ions tests have shown a BER of 5.19e-8.

This paper presents the design and the experimental characterization of a 10 Gb/s electronic driver for silicon Mach-Zehnder modulators (MZMs). This driver is able to operate in harsh environments characterized by radiation levels up to 1 Grad(SiO ₂ ) total ionizing dose (TID). To compensate for the detrimental effects that radiation produces on the target 65 nm bulk silicon technology both device- and circuit-level radiation hardened by design (RHBD) techniques are developed and implemented. Extreme TID levels are faced using long-channel transistors with enclosed layout, avoiding the use of p-MOSFETs, and implementing a differential self-biased cascode architecture with common-mode feedback. Band-widening techniques, e.g., inductive peaking, cross-coupled capacitors, and buffer chaining, have been used to improve the driver’s frequency response and reach the targeted data rate. Electrical measurements show 10 Gb/s waveforms with an eye diagram amplitude suitable for MZM driving. Electro-optical measurements performed connecting the electronic driver to a silicon photonic MZM confirm the achievement of a 10 Gb/s system-level operability. The radiation hardness of the driver is verified by exposing the integrated circuit to X-rays. The measurements confirm the ability of the driver to work up to 1 Grad with an eye amplitude reduction of only 10% and a 7% increment in the rise and fall times, validating the effectiveness of the implemented RHBD techniques.

This paper presents the design and verification of electromagnetic interference (EMI) reduction techniques for switching dc/dc converters. A 48-V dc/dc converter for electric/hybrid cars is considered as an application case study. An EMI filter with a very low inductor value is designed to reduce the overvoltage issues. The proposed design procedure takes into account the converter impedance and the cable model in order to avoid the state-of-the-art tendency of oversizing the filter components. Thus, the filter implementation is simplified and its EMI reduction capability is kept unaltered. Measurements of near EM field in anechoic room show that, using a low switching frequency for the dc/dc converter, the EMI problem is shifted from radiated to conducted emissions. A SKIP-mode modulation technique is implemented to control the converter output and also to reduce the conducted EMI, as shown by CAD simulations and experimental measurements. In addition, a soft-start technique, which reduces by three times the currents' spikes, is integrated into the dc/dc converter to minimize the EMI at the car's starting.

Sidelobes in the two-way radiation pattern are of serious concern in a radar array. Several techniques have evolved to mitigate the problem, which include amplitude tapering, Genetic Algorithm (GA) optimization, thinning transceiver aperture, and two-weight amplitude distribution. With such optimization schemes, the sidelobes can be considerably suppressed but at the cost of a reduction in directivity or taper efficiency. Further, such amplitude tapers require a complex feeding network design. This work alleviates such design restrictions and proposes a systematic approach to lower the sidelobes in radar two-way shared aperture arrays. The proposed methodology can achieve a sidelobe level (SLL) of below -52 dB in both linear and planar arrays, which is about 18 dB enhancement in SLL compared with uniform transmit and thinned receive arrays. In addition, as a result of the equal transceiver array size in the proposed design, an improvement of approximately 0.44 dB and 0.68 dB in directivity is achieved in linear and planar arrays, respectively. A novel feeding architecture is also illustrated to reduce the cost and complexity of the overall feeding network. A set of full-wave simulations have also been performed to validate the theoretical results.

The experimental characterization through electrical, electromagnetic, and thermal measurements of a new dc/dc converter architecture for high-voltage inputs, up to 60 V, is proposed in this paper. The converter has a new multistage integrated circuit (IC) topology, where each stage is inductorless and exploits a switched capacitor solution. The dc/dc converter was implemented in multiple configurations, using a ceramic package or a naked die (directly glued on the testing board), with passive devices stacked on the top of the IC, through an interposer (3-D technology), or mounted near the IC in the testing board (2-D version). The measurement activity in terms of line and load regulations, power supply rejection ratio, electrostatic discharge protection, conductive and radiated electromagnetic interference, efficiency, and thermal behavior, allows analyzing the effects of different circuits and technology choices. The achieved results prove the suitability of the integrated dc/dc converter, using 3-D technology, for applications where low-power loads (e.g., sensors, memories, and processors) have to be supplied by high-voltage power supplies, such as car's electronic control units in 48-V electric/hybrid vehicles.