Tong Xingyuan

Prof. Tong Xingyuan


Research Focus & Metrics

Academic Career Length

17Years (2010-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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7 January 2019 in IEEE Transactions on Biomedical Circuits and Systems
Verified
Journal Article
Closed access
Byunghun LeeByunghun Lee
Byunghun Lee
Yaoyao JiaYaoyao Jia
Yaoyao Jia
SMS. Abdollah Mirbozorgi
S. Abdollah Mirbozorgi
MCMark Connolly
Mark Connolly
TXTong Xingyuan
Tong Xingyuan
MGMaysam Ghovanloo
Maysam Ghovanloo
An inductively-powered wireless integrated neural recording and stimulation (WINeRS-8) system-on-a-chip (SoC) that is compatible with the EnerCage-HC2 for wireless/battery- less operation has been presented for neuroscience experiments on freely behaving animals. WINeRS-8 includes a 32-ch recording analog front-end (AFE), a 4-ch current-controlled stimulator, and a 434 MHz on-off keying (OOK) data link to an external software- defined radio (SDR) wideband receiver (Rx). The headstage also has of a Bluetooth Low Energy (BLE) link for controlling the SoC. WINeRS-8/EnerCage-HC2 systems form a bidirectional wireless and battery-less neural interface within a standard homecage, which can support longitudinal experiments in an enriched environment. Both systems were verified in vivo on rat animal model, and the recorded signals were compared with hardwired and battery-powered recording results. Real-time stimulation and recording verified the system's potential for bidirectional neural interfacing within the homecage, while continuously delivering 35 mW to the hybrid WINeRS-8 headstage over an unlimited period.

1 July 2015 in Electronics Letters
Verified
Journal Article
Open access
PDF file
TXTong Xingyuan
Tong Xingyuan
YZYang Zhang
Yang Zhang
An energy‐efficient successive approximation register (SAR) analogue‐to‐digital converter (ADC) switching scheme is proposed for low‐power biomedical applications. By dramatically reducing energy consumption in the first three bit‐cycles, the average switching energy of the proposed scheme is reduced by 98.8% compared with the conventional architecture. The number of capacitors in the capacitor array of this proposed scheme is also reduced by 75.5% over the conventional approach.

1 April 2015 in Electronics Letters
Verified
Journal Article
Open access
PDF file
TXTong Xingyuan
Tong Xingyuan
MGMaysam Ghovanloo
Maysam Ghovanloo
An energy‐efficient switching scheme for a low‐power successive approximation register (SAR) analogue‐to‐digital converter (ADC) is proposed. Taking the parasitic capacitance of the capacitor array into consideration, the average switching energy of the proposed scheme can be reduced by 97.4% compared with the conventional architecture. The proposed scheme also reduces the number of capacitors in the capacitor array by 75.5% and hence achieves area efficiency with high performance.

13 May 2019 in Circuits, Systems, and Signal Processing
Verified
Journal Article
Closed access
PDF file
TXTong Xingyuan
Tong Xingyuan
MSMengdi Song
Mengdi Song
YCYawen Chen
Yawen Chen
SDSiwan Dong
Siwan Dong

12 April 2014 in Analog Integrated Circuits and Signal Processing
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Journal Article
Closed access
PDF file
TXTong Xingyuan
Tong Xingyuan
WZW. P. Zhang
W. P. Zhang
FLF. X. Li
F. X. Li

29 March 2022 in Circuits, Systems, and Signal Processing
Verified
Journal Article
Closed access
PDF file
XXXin Xin
Xin Xin
YHYuanhao Hu
Yuanhao Hu
JCJueping Cai
Jueping Cai
SDSiwan Dong
Siwan Dong
TXTong Xingyuan
Tong Xingyuan