This paper proposes an image encryption scheme using the combination of chaos, hyper-chaos, and DNA sequence operation. The proposed scheme performs three stages of encryption operations. Those are selection-level hyper-chaotic sequence based DNA-shuffling operation, key-image based DNA-diffusion operation, and hyper-chaotic sequence based DNA-shuffling operation. The advantages of this scheme are higher key space, higher confusion or randomness of pixels, higher sensitivity to the keys and plaintext pixels, stronger resistivity to the noises, and lossless encryption and decryption. Moreover, selection-level hyper-chaotic sequence based DNA-shuffling operation generates more complexities in the confusion process which increases the strength of encryptions and decryptions. The computer simulation and security analyses confirm the good encryption results of the proposed scheme and strong resistivity to the commonly used attacks.

This paper proposes a 4-bit array multiplier useful in the design of basically mixer circuit, which is highly involved in signal and image processing using an efficient low-power VLSI technique. The presented architecture is completely implemented adiabatic techniques in the Near Threshold Region, which optimize the product of propagation delay and power dissipation. Multiplier is the most frequently used element in many digital electronics applications. Depending on the applications, various types of multipliers emerge. With this technique, the total power dissipation, i.e. dynamic power dissipation as well as static power dissipation is less as compared to the conventional CMOS technique. The Near Threshold Adiabatic Logic (NTAL) technique is used with a single timevarying power supply which reduces the clock tree management and enhances the energy-saving capability. Simulation of the proposed design is done by Cadence virtuoso schematic editor with specter simulator on TSMC 65 nm technology node to verify the optimized result. Also comparing our result to conventional CMOS techniques with all the same design parameters, the result shows that power dissipation improvement of approximately 66.6%, 14.4%, and 64.6% with respect to varying frequency, supply voltage, and load capacitance with other parameters keep constant such as if the frequency is varying than capacitance load value is C_load = 10 pF and V_DD(max)= 1.2 V, similarly if the supply voltage is varying than capacitance load value is C_load = 10 pF and frequency F = 4 GHz and if load capacitance is varying than frequency F = 4 GHz and supply voltage V_DD(max)= 1.2 V.