This article presents a four-level pulse-amplitude modulation (PAM-4) transceiver targeting very-short-reach and medium-reach (MR) electrical links. The receiver (RX) employs a sample-based four-tap feed-forward equalizer (FFE) for pre-and post-cursor inter-symbol interference (ISI) compensation. The two-stage 16-way interleaving provides sufficient operation time for FFE summation, which relaxes the bandwidth (BW) requirement and improves power efficiency. The non-uniform segmented three-tap FFE reduces the parasitic capacitance in the transmitter (TX). The one-unit interval (UI)-pulse generator in the 4:1 multiplexer uses a pre-charge phase to achieve a fast edge with single-stage logic. Fabricated in 28-nm CMOS technology, the transceiver achieves a bit error rate (BER) of $<$ 1 $e-11$ at 112-Gb/s transmission with a channel loss of 20.8 dB and an energy efficiency of 2.29 pJ/b.

A hardware‐efficient slope‐error (SE) algorithm based four‐level pulse amplitude modulation (PAM4) baud rate clock and data recovery (CDR) scheme is proposed. The algorithm uses three adjacent data information to obtain slope information, thus reduces the required error samplers by 75% compared to the widely used baud rate CDR, namely, Mueller Müller (MM) CDR when working at same phase detector (PD) gain. The power efficiency of the CDR loop is improved by 36% compared to MM CDR. The proposed PAM4 baud rate CDR does not bring in extra block except for PD, which makes it easy to be extended from adaptive decision feedback equalisation. A 40 Gb/s PAM4 receiver with the proposed CDR is designed in 55 nm CMOS process. The simulated jitter tolerance of the CDR at high frequency exceeds the SONET OC‐768 JTOL mask by at least 0.35 UI at the bit error rate of 10 ⁻¹² . The CDR loop consumes 106 mW from a 1.2 V supply and occupies an active area of 0.1 mm ² .

This article presents a five-tap delay-line-based feed-forward equalizer (FFE) for 200-Gb/s wireline receiver (RX) in 28-nm CMOS technology. The RX FFE employs on-chip grounded coplanar waveguides (GCPWs) as delay lines and a one-stage topology for higher bandwidth and lower power. Two large taps are implemented with distributed amplifiers to alleviate reflection. Cross-connected variable-transconductance cells improve linearity for small coefficients. RC source degeneration in the variable-transconductance cell provides low-frequency equalization that reduces the number of taps. Measurement results indicate that the FFE can equalize the 200-Gb/s data after a 17.2-dB loss channel with an energy efficiency of 0.42 pJ/b. It can also work as a fractional-spaced FFE for the 150-, 100-, and 50-Gb/s data. To the best of our knowledge, this work is the first continuous-time FFE operating at 200 Gb/s.

Coherent detection with polarization multiplexing is widely used because of its high spectral efficiency. However, it utilizes analog-to-digital converters (ADCs) and digital signal processing (DSP), which consume a large amount of power and thereby hinder its application in power-sensitive short-reach links. In this article, we present a 200-Gb/s analog $C$ -band dual-polarization quadrature phase shift keying (DP-QPSK) coherent optical receiver (RX), which uses four-way time-interleaved sampling to relax the internal bandwidth limit. The RX utilizes a chromatic dispersion (CD) equalizer, a polarization demultiplexer (Pol. DEMUX), and carrier recovery (CR) to eliminate the intersymbol interferences induced by fiber impairments and the carrier frequency offset. A subsampling scheme is adopted for low-power adaptation. The decrease in the frequency offset detection range caused by subsampling is prevented using a consecutive slice sampling technique. Measurement results show that our RX supports equalization for impairments equivalent to a 10-km fiber and CR for a residual carrier frequency offset of 12 MHz. A bit error rate (BER) of less than $1e-10$ is achieved with an energy efficiency of 4.6 pJ/b.

This paper presents a clock-feedthrough compensation technique for bootstrapped switches. The proposed technique utilizes a dummy transistor to generate a reverse voltage, which compensates the input-dependent error caused by clock feedthrough effect of sampling switch. Simulation result shows the differential sampling error of bootstrapped switch reduces from 7.2mV to 1.4mV for the worst case, operating at 500MHz sampling speed in 55nm CMOS technology with a 300fF hold capacitor. The bootstrapped switch consumes 27uW power with only 1.5uW in compensation.