In this article, we investigate the self-heating effect (SHE) of the Complementary FET (CFET) device and propose a cross-coupled thermal network model. For the investigation of thermal behavior, the intra- and inter-device crosstalk of CFET is evaluated qualitatively through the defined crosstalk coefficient. The results indicate that CFETs have more severe intra-device thermal crosstalk, almost twice that of CMOS. Moreover, the vertical structure makes the heat dissipation path of CFET devices significantly different in the two transition states (inputs ``1'' and ``0''). Based on the thermal behavior characteristics of CFET and the necessity of high-precision and rapid prediction of thermal characteristics of the devices, a thermal network model is proposed, which can quickly respond to the heat source and be extended at the array level. In the last part, we analyze the influence of load capacitance and operating frequency on the self-heating of CFET, and SHE-related reliability lifetime is predicted based on the lattice temperature obtained from the thermal network. The prediction results show that the bias temperature instability (BTI) lifetime of CFET degrades by 84% compared with standard CMOS.

This article presents a four-level pulse-amplitude modulation (PAM-4) transceiver targeting very-short-reach and medium-reach (MR) electrical links. The receiver (RX) employs a sample-based four-tap feed-forward equalizer (FFE) for pre-and post-cursor inter-symbol interference (ISI) compensation. The two-stage 16-way interleaving provides sufficient operation time for FFE summation, which relaxes the bandwidth (BW) requirement and improves power efficiency. The non-uniform segmented three-tap FFE reduces the parasitic capacitance in the transmitter (TX). The one-unit interval (UI)-pulse generator in the 4:1 multiplexer uses a pre-charge phase to achieve a fast edge with single-stage logic. Fabricated in 28-nm CMOS technology, the transceiver achieves a bit error rate (BER) of $<$ 1 $e-11$ at 112-Gb/s transmission with a channel loss of 20.8 dB and an energy efficiency of 2.29 pJ/b.

Erbium-doped materials have played an important role in the fabrication of light sources used in silicon photonics. Recent studies demonstrated that erbium silicate nanowire had a high net gain attributable to its high erbium concentration and excellent material quality. We establish a more accurate and comprehensive theoretical model of erbium silicate nanowire, analyze the modeled nanowire’s properties, and optimize a high-gain erbium silicate waveguide amplifier and low-threshold, high-efficiency laser by considering upconversion, energy transfer, and amplified spontaneous emission. The simulation results and previous experimental data reported in reference showed some agreement. A proposed waveguide amplifier, based on the optimized design, displayed a gain greater than 20 dB/mm. Then, a 3.3 mW low-threshold laser with a maximum power-conversion efficiency of 50% was modeled by choosing the optimized resonator cavity and reflector. The results indicate that erbium silicate compound materials with large optical gains can serve as potential candidates for inclusion in scale-integrated amplifiers and other applications requiring lasers.

A frame differencing pixel (FDP) design based on fully depleted silicon-on-insulator (FD-SOI) technology is presented, demonstrating the capability of the FDP to perform pixel-level real-time frame difference (FD) for motion extraction and image preprocessing. The photo charges are collected by the diode under the buried oxide (BOX) and sensed by the MOSFET above. The capacitance of the BOX is used to generate the FD signal without incurring more area costs. TCAD simulations of the FD-SOI FDP were performed to help the analysis. An optimal pixel design model was developed to describe the relationship between noise performance and area allocation. According to the simulation results, the FDP could achieve light sensitivity of $25.6 ~\mu \text{A}$ /( $\mu \text{J}$ /cm2) and a differential signal-to-noise ratio of 35 dB with a $4 ~\mu \text{m}$ pixel pitch and 76% fill factor.

This article presents a five-tap delay-line-based feed-forward equalizer (FFE) for 200-Gb/s wireline receiver (RX) in 28-nm CMOS technology. The RX FFE employs on-chip grounded coplanar waveguides (GCPWs) as delay lines and a one-stage topology for higher bandwidth and lower power. Two large taps are implemented with distributed amplifiers to alleviate reflection. Cross-connected variable-transconductance cells improve linearity for small coefficients. RC source degeneration in the variable-transconductance cell provides low-frequency equalization that reduces the number of taps. Measurement results indicate that the FFE can equalize the 200-Gb/s data after a 17.2-dB loss channel with an energy efficiency of 0.42 pJ/b. It can also work as a fractional-spaced FFE for the 150-, 100-, and 50-Gb/s data. To the best of our knowledge, this work is the first continuous-time FFE operating at 200 Gb/s.

In always-on edge devices, the static leakage current in weights retention accounts for a significant proportion of power consumption. Furthermore, the analog-to-digital converter (ADC) module consumes a lot of area and power in most computing-in-memory (CIM) architectures. Therefore, this design presents an 8 Kb time-domain (TD) CIM macro with low static leakage. In addition, this work takes advantage of the scalability of TD-CIM and presents a precision-configurable time-to-digital converter (TDC) applied to scenarios that require adjustable accuracy. It achieves configurable precision of 2 to 4 bits with a multiplication-and-accumulation (MAC) range of 32 in each delay chain. The TDC module accounts for only 2.9% of the total macro area, achieving nearly a tenfold improvement over prior works. The measured normalized energy efficiency is 768.7-2124.2 TOPS/W. The static leakage of the macro is 206 fW/bit while VDD is 1.2 V. This work achieves 91.1%-86.1% inference accuracy on the CIFAR-10 dataset with 8-bit precision in inputs and weights.