The lack of effective methods to develop the product, process and operation models based on virtual and physical convergence leads to the poor performance on intelligence, real-time capability and predictability in production management. This paper proposes an approach of modelling and operations for the digital twin in the context of manufacturing. Firstly, the concept and extension of the digital twin in the manufacturing context are elaborated to provide the implementation methods of virtual-physical convergence and information integration for a factory. Secondly, the modelling approaches of product digital twins, process digital twins and operation digital twins are presented, then the interoperation mode between these digital twins are explained. Thirdly, to elaborate how to execute operations between product, process and resource, Automation Markup Language (AutomationML) is used for modelling a structural parts machining cell. Finally, the performance evaluation is provided to demonstrate the improvement of production efficiency by using the proposed approach.

Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries. During wafer fabrication, several types of defects can be coupled together in a piece of wafer, it is called mixed-type defects DPR. To detect mixed-type defects is much more complicated because the combination of defects may vary a lot, from the type of defects, position, angle, number of defects, etc. Deep learning methods have been a good choice for complex pattern recognition problems. In this paper, we propose a deformable convolutional network (DC-Net) for mixed-type DPR (MDPR) in which several types of defects are coupled together in a piece of wafer. A deformable convolutional unit is designed to selectively sample from mixed defects, then extract high-quality features from wafer maps. A multi-label output layer is improved with a one-hot encoding mechanism, which decomposes extract mixed features into each basic single defect. The experiment results indicate that the proposed DC-Net model outperforms conventional models and other deep learning models. Further results of the interpretable analysis reveal that the proposed DC-Net can accurately pinpoint the defects areas of wafer maps with noise points, which is beneficial for mixed-type DPR problems.

Forecasting short-term cycle time of wafer lots is crucial for production planning and control in the wafer manufacturing. A novel recurrent neural network called bilateral long-short-term memory (bilateral LSTM) is proposed to model a short-term cycle time forecasting (CTF) of each re-entrant period of a wafer lot. First, a two-dimensional architecture is designed to transmit the wafer and layer correlations by using wafer and layer connections. Subsequently, aiming to store various error signals caused by the diverse CT data, a multiply memory structure is presented to extend the capacity of constant error carousel (CEC) in the LSTM model. The experiment results indicate that the proposed model outperforms BPN, SVR, and MLR in the accuracy and stability for the short-term CTF. Further comparative experiments reveal that the two-dimensional architecture can enhance the prediction accuracy and the multi-CEC structure can improve the forecasting stability for the short-term CTF of wafer lots.

In order to improve the prompt delivery reliability of the semiconductor wafer fabrication system, a big data analytics (BDA) is designed to predict wafer lots’ cycle time (CT), which is composed by four parts: data acquisition, data pre-processing, data analysing and data prediction. Firstly, the candidate feature set is constructed to collecting all features by analysing the material flow of wafer foundry. Subsequently, a data pre-processing technique is designed to extract, transform and load data from wafer lot transactions data-set. In addition, a conditional mutual information-based feature selection process is proposed to select key feature subset to reduce the dimension of data-set through data analysing without pre-knowledge. To handle the large volumes of data, a concurrent forecasting model is designed to predict the CT of wafer lots in parallel as well. According to the numerical analysis, the predict accuracy of the presented BDA improves clearly with the increase in data size. And, in the large-scale data-set, the BDA has higher accuracy than linear regression and back-propagation network in CT forecasting.

Accurate prediction of cycle time (CT) plays an important role in the promises of a good delivery-time for semiconductor manufacturers. However, the CTs of wafer lots are difficult to forecast since they are influent by a lot factors (e.g., workload for every machine). The identification of key factors (called CT-related) can not only improve the prediction performance but also facilitate the control of CT, which is of particular significance. This paper focuses on gathering subtle variables into the candidate variables set along with the further analysis which is required in the correlation analysis between various candidate factors and CTs of wafer lots. The candidates set is first constructed to collect all factors that may affect wafer lots’ CT. Then, a regression-based model is proposed to select CT-related variables, which consists of three parts: 1) discretization; 2) adaptive logistic regression-based correlation analysis; and 3) CT-related factor selection. Subsequently, a parallel computation model is implemented to forecast the CTs of wafer lots. In the numerical experiments, 108 CT-related factors stood out from 774 candidates and replaced six global factors (used as reference) to predict CTs of wafer lots. The results indicated that the proposed approach had higher accuracy than linear regression and back propagation network in CT forecasting in large scale data analysis.