Experimental results gained by various electrical characterization techniques are discussed and compared for a CNTFET technology, which suffers as almost all emerging technologies from traps in the gate oxide. Based on these results, it is highlighted that, contrary to common practice, a fast data acquisition technique is required to ensure a proper electrical device characterization in terms of 1) trap-free device characteristics, 2) reproducible experimental results, and 3) a consistent set of dc and small-signal (ac) characteristics. It is argued that a reasonable technology comparison among emerging technologies must be based on data fulfilling these criteria since trap-affected measurements distort the device behavior which can lead to wrong conclusions about the performance of a device such as the apparent linearity. A trap model capturing the aforementioned issues is briefly introduced. Moreover, the challenges of the electrical characterization of high-impedance devices are explored.

During the recent years, a significant amount of research has been performed on single-walled carbon nanotubes (SWCNTs) as a channel material in thin-film transistors (Pham et al. IEEE Trans Nanotechnol 11:44–50, 2012). This has prompted the application of advanced characterization techniques based on combined atomic force microscopy (AFM) and Raman spectroscopy studies (Mureau et al. Electrophoresis 29:2266–2271, 2008). In this context, we use confocal Raman microscopy and current sensing atomic force microscopy (CS-AFM) to study phonons and the electronic transport in semiconducting SWCNTs, which were aligned between palladium electrodes using dielectrophoresis (Kuzyk Electrophoresis 32:2307–2313, 2011). Raman imaging was performed in the region around the electrodes on the suspended CNTs using several laser excitation wavelengths. Analysis of the G+/G− splitting in the Raman spectra (Sgobba and Guldi Chem Soc Rev 38:165–184, 2009) shows CNT diameters of 2.5 ± 0.3 nm. Neither surface modification nor increase in defect density or stress at the CNT-electrode contact could be detected, but rather a shift in G+ and G− peak positions in regions with high CNT density between the electrodes. Simultaneous topographical and electrical characterization of the CNT transistor by CS-AFM confirms the presence of CNT bundles having a stable electrical contact with the transistor electrodes. For a similar load force, reproducible current–voltage (I/V) curves for the same CNT regions verify the stability of the electrical contact between the nanotube and the electrodes as well as the nanotube and the AFM tip over different experimental sessions using different AFM tips. Strong variations observed in the I/V response at different regions of the CNT transistor are discussed.

For an industrial realization of devices based on single-walled carbon nanotube (SWCNTs) such as field-effect transistors (FETs) it becomes increasingly important to consider technological aspects such as intrinsic device structure, integration process controllability as well as yield. From the perspective of a wafer-level integration technology, the influence of SWCNT length on the performance of short-channel CNT–FETs is demonstrated by means of a statistical and comparative study. Therefore, a methodological development of a length separation process based on size-exclusion chromatography was conducted in order to extract well-separated SWCNT dispersions with narrowed length distribution. It could be shown that short SWCNTs adversely affect integrability and reproducibility, underlined by a 25% decline of the integration yield with respect to long SWCNTs. Furthermore, it turns out that the significant changes in electrical performance are directly linked to a SWCNT chain formation in the transistor channel. In particular, CNT–FETs with long SWCNTs outperform reference and short SWCNTs with respect to hole mobility and subthreshold controllability by up to 300% and up to 140%, respectively. As a whole, this study provides a statistical and comparative analysis towards chain-less CNT–FETs fabricated with a wafer-level technology.