The progress made toward the definition of a modular compact modeling technology for graphene field‐effect transistors (GFETs) that enables the electrical analysis of arbitrary GFET‐based integrated circuits is reported. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Another set of secondary models accounts for the GFET non‐idealities, such as extrinsic‐, short‐channel‐, trapping/detrapping‐, self‐heating‐, and non‐quasi static‐effects, which can have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, a perspective of the challenges during the scale up of the GFET modeling technology toward higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers, is provided.

A compact large-signal model, called Compact Carbon Nanotube Model (CCAM), is presented that accurately describes the shape of DC and small-signal characteristics of fabricated carbon nano-tube FETs (CNTFETs). The new model consists of computationally efficient and smooth current and charge formulations. The model allows, for a given gate length, geometry scaling from single-finger single-tube to multifinger multitube transistors. Ambipolar transport, temperature dependence with self-heating, noise, and a simple trap model have also been included. The new model shows excellent agreement with the data from both the Boltzmann transport equation and measurements of Schottky-barrier CNTFETs and has been implemented in Verilog-A, making it widely available across circuit simulators.

Experimental results gained by various electrical characterization techniques are discussed and compared for a CNTFET technology, which suffers as almost all emerging technologies from traps in the gate oxide. Based on these results, it is highlighted that, contrary to common practice, a fast data acquisition technique is required to ensure a proper electrical device characterization in terms of 1) trap-free device characteristics, 2) reproducible experimental results, and 3) a consistent set of dc and small-signal (ac) characteristics. It is argued that a reasonable technology comparison among emerging technologies must be based on data fulfilling these criteria since trap-affected measurements distort the device behavior which can lead to wrong conclusions about the performance of a device such as the apparent linearity. A trap model capturing the aforementioned issues is briefly introduced. Moreover, the challenges of the electrical characterization of high-impedance devices are explored.

Exploiting ambipolar electrical conductivity based on graphene field‐effect transistors has raised enormous interest for high‐frequency (HF) analog electronics. Controlling the device polarity, by biasing the graphene transistor around the vertex of the V‐shaped transfer curve, enables to redesign and highly simplify conventional analog circuits, and simultaneously to seek for multifunctionalities, especially in the HF domain. This study presents new insights for the design of different HF applications such as power amplifiers, mixers, frequency multipliers, phase shifters, and modulators that specifically leverage the inherent ambipolarity of graphene‐based transistors.

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-reduced experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the trap effects on the channel potential within the device. High-frequency (HF) figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and HF applications.