We demonstrate smart contact lenses for noninvasive and continuous diabetic diagnosis and diabetic retinopathy therapy.

This article presents a controller IC for smart contact lens (SCL). For wireless telemetry, we propose a transmitter supporting dual-mode operations with a single external loop antenna. In the wireless-powered backscattering load-shift keying (LSK) mode, the transmitter is configured to use the antenna as an L for magnetic resonance coupling. The transmitter switches its configuration to be an active LC oscillator circuit in the RF-radiated transmission mode. To suppress the average power consumption, a 0.2% duty cycling is applied with a controlled timing schedule while minimizing static power consumption in the sleep mode. To reduce the effect of instantaneous discharging, the period of data transmission is shortened by transmitting data with a higher rate. The designed IC is fabricated using 0.18-μm CMOS. For in vitro verifications in both modes, an SCL is implemented by integrating the IC, a glucose sensor, a thin-film battery, a loop antenna, and a supply-regulating capacitor. The IC achieves a power consumption of 143 nW with an input dynamic range of 89 dB.

This article proposes a circuit architecture and design strategy of a low-noise oscillator based on the distributed RC network. The distributed RC network receives a differential step input and propagates the true phase through the resistive path while the complementary phase through the capacitive path. It effectively suppresses the effect of noise by increasing the signal transition slope at the time of interest. It is achieved by embedding a bandpass characteristic with a phase delay of $\pi $ . A 358-kHz quadrature oscillator with a fourth-stage RC network is implemented using the 0.18- $\mu \text{m}$ CMOS process. It achieves an figure of merit (FoM) of −161.2 dBc/Hz at a 100-Hz offset with a stable 20-dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm.

This paper presents a fully differential distributed RC oscillator implemented within a frequency-locked loop (FLL). It employs a frequency error detector in the differential distributed RC network to boost the transition slopes while staying within supply rails in the feedback loop, thereby increasing the frequency-to-voltage gain and mitigating overall noise. The design also features a second-order temperature compensation that integrates a coarse 4 b temperature sensor, polynomial calculation, and a Delta-Sigma Modulator (DSM) to regulate the reference voltage over temperature. Fabricated in 0.18 lm CMOS, the 1.26 MHz oscillator achieves an rms period jitter of 89.9 ps (0.011 %), an Allan deviation floor of 0.52 ppm, and temperature sensitivities of 7.14 ppm/0C for second-order, while consuming 252 lW at a supply voltage of 1.8V.

Split capacitor digital-to-analog converters (split-CDACs) are a promising method to reduce area but face challenges with parasitic sensitivity in high-resolution settings for successive approximation register analog-to-digital converters (SAR ADCs) design. This article introduces a split-CDAC design for improving area efficiency for higher bit resolution by reducing parasitic sensitivity and mismatch. A fundamental reason for the increased parasitic sensitivity stems from the fractional sizing of the bridge capacitor and a small redundant capacitor at the split node. The proposed split-CDAC uses a unit capacitor-based bridge capacitor and a proportionally scaled large redundant unit capacitor, which minimizes these effects to a large extent while achieving linearity. It achieves six times better parasitic sensitivity than a conventional split-CDAC by using six-unit capacitors as a bridge capacitor and 12 times better area efficiency than the conventional binary-weighted CDAC. The proposed fully common-centroided and shielded unit capacitor array, implemented in a 65 nm CMOS process, effectively reduces parasitic and mismatch sensitivity using a simple layout structure. The implementation achieves an INL of less than 1.2 LSB, measured across 21 chips, without mismatch calibration and opens new possibilities for high-precision applications across diverse domains.