This article presents a controller IC for smart contact lens (SCL). For wireless telemetry, we propose a transmitter supporting dual-mode operations with a single external loop antenna. In the wireless-powered backscattering load-shift keying (LSK) mode, the transmitter is configured to use the antenna as an L for magnetic resonance coupling. The transmitter switches its configuration to be an active LC oscillator circuit in the RF-radiated transmission mode. To suppress the average power consumption, a 0.2% duty cycling is applied with a controlled timing schedule while minimizing static power consumption in the sleep mode. To reduce the effect of instantaneous discharging, the period of data transmission is shortened by transmitting data with a higher rate. The designed IC is fabricated using 0.18-μm CMOS. For in vitro verifications in both modes, an SCL is implemented by integrating the IC, a glucose sensor, a thin-film battery, a loop antenna, and a supply-regulating capacitor. The IC achieves a power consumption of 143 nW with an input dynamic range of 89 dB.

Designing analog circuits incurs high time costs because designers must consider numerous design variables or trade-off relationships of circuit performance based on a lot of knowledge and experience. To reduce design time, various machine learning methods have been used to optimize analog circuits by learning the correlation between the device size and the circuit performance. However, it is difficult to train the correlation because of its high non-linearity and wide design space. In this paper, this study proposes a new framework to optimize analog circuit designs by combining reinforcement learning (RL) and the sensitivity analysis with g m /I D sizing, which is more intuitive for interpreting circuit performance. Furthermore, the universal value function approximator (UVFA), previously proposed in RL, is modified more simply to make it easier to find the target design. Additionally, the dataset is rearranged and sampled by the criteria that are established based on the principle of circuit operation, which helps to orient the agent to learn the circuit operation. Using the proposed methods, we optimize three types of differential amplifiers with common mode feedback circuits and obtain the best circuit design. Compared to baseline, we find the optimal point using modified UVFA, and moreover, reduce the number of iterations by 42.2%, 39.5%, and 37.5%, respectively, for the three test cases.

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit that utilizes common-mode clock-embedded signaling (CM-CES) and injection locking techniques to reduce design complexity for the half-rate data recovery. In the proposed receiver, the use of wideband injection-locked oscillator (ILO) greatly suppresses its phase noise while the narrowband digital phase tracking loop (DPTL) tunes retiming phase. For wide-range and continuous-rate operation, four circuit techniques have been adopted: a VCO with active inductance load for low VCO gain at high frequency, a wide-range digitally-controlled delay line (DCDL) with adaptive band selection, a linearized delay control unit with CM-to-delay conversion technique, and a coarse frequency detection scheme to drive the free-running oscillator frequency toward injection locking. The prototype CDR, fabricated in low power CMOS 65 nm technology, successfully detects 0.8-6.5 Gb/s data rates over 5" FR4 trace with 2 ³¹ -1 PRBS pattern satisfying BER <; 10 ^-12 . The power efficiency was 2.4 mW/Gb/s at 6.5 Gb/s.

This paper describes the characteristics of a half-rate clock-embedded source-synchronous signaling scheme to identify its constraints and to optimize the transceiver topology in the presence of a band-limited channel. The proposed signaling combines the half-rate clock to the common mode of the differential data with its mixing phase off by 0.5 UI. Two transceivers with resistive-load and inductive-load receivers are implemented in 130-nm CMOS technology to verify their feasibility for use as serial links. The prototype transceivers achieve a wide operating frequency range 2.25-6 and 5.6-8 Gb/s, respectively, satisfying bit error rate of <;10^-12 measured at Tx-Rx linked configuration by 5-in-long FR4 trace with 2³¹-1 PRBS. The power efficiencies of transceivers at maximum data rates are 6.4 and 4.6 mW/Gb/s, respectively.

This article presents a 20-Gb/s/line current-mode (CM) transceiver for dense short-reach on-chip interconnect. The transceiver achieves a systematic crosstalk cancellation (XTC) by balancing the capacitive and inductive coupling. As a receiver frontend, a current-sensing amplifier is designed with an optimum input resistance value for XTC. Without any additional circuits for XTC and equalization, the transceiver implemented in a 40 nm CMOS technology shows a data rate of 20 Gb/s/line and an energy efficiency of 246 fJ/b, even with shield-less dense channels with 1.5- $\mu $ m pitch. In addition, this article analyzes the crosstalk for dense short-reach channels and establishes the theorem of coupling-balanced XTC (CBXTC).