High-frequency digitally controlled dc–dc switching converters have many advantages, such as very fast transient response and high-power density. However, the studies of control strategies and algorithms specifically for high-frequency digitally controlled dc–dc converters are seldom reported. In this study, we propose a novel digital current-mode controller consisting of both output voltage and inductor current compensators for high-frequency dc–dc switching converters. The voltage compensator is designed based on the delta operator instead of the shift operator, which could improve the control accuracy and reduce hardware costs. Furthermore, the current compensator is designed using an advanced sampling predictive (ASP) control strategy to reduce the requirement of hardware processing speed, and in turn the hardware cost, and to eliminate the influences of noise caused by power switch commutations. Finally, a buck dc–dc switching converter with a switching frequency of 2 MHz is designed and implemented using the proposed digital current-mode controller on a field-programmable gate array (FPGA) platform. Our test results indicate that better control accuracy and lower hardware costs can be realized using the delta operator instead of using the shift operator. In addition, compared with the single digital voltage compensator, the proposed digital current-mode controller has better transient response performances. The control strategy and algorithm proposed in this study are especially effective for digitally controlled high-frequency dc–dc switching converters.

In this paper, we present the design and preliminary results of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for a PET imaging system whose objective is to achieve the following performances: the spatial resolution of 1 mm ³ , the detection efficiency of 15% and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. An eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm ×2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy level of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC. The tested result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3%. The crosstalk is less than 2%. The power dissipation is about 3 mW/channel.

Both the stability and the control accuracy of digital controllers for DC–DC switching converters utilising shift operators severely degrade under high switching frequencies. This study presents a digital‐proportion integration differentiation (D‐PID) controller based on a delta operator for DC–DC converters with high switching frequencies. Both the stability and the control accuracy of the digitally controlled converters were effectively improved when using the delta operator instead of the shift operator. The hardware cost and the processing speed requirements were also considerably reduced. The performance advantages of such a D‐PID controller were theoretically analysed, and then simulated using the Simulink platform. Finally, both the proposed D‐PID controller and a conventional shift operator‐based controller were implemented for DC–DC switching converters on a field‐programmable gate array (FPGA) platform. The benefits of using the delta operator over the shift operator were experimentally verified, and the test results indicated that for the DC–DC switching converter with 2 MHz switching frequency, better control accuracy can be obtained by using the delta operator than using the shift operator.

Owing to its fast transient response, the V ² control technique for switching converters has wide potential application prospects. In this article, we present a digital V ² controller integrated circuit (IC) for dc–dc switching converters to improve the transient response. The controller IC consists of two compensators and some ancillary circuits, specifically a proportion-integral-differential (PID) compensator and a predictive control compensator, as well as an analog-to-digital converter (ADC) and a digital pulsewidth modulator (DPWM). The PID compensator is designed based on the delta operator instead of the conventional shift operator, which can improve the stability of the converter and reduce hardware costs. The predictive control compensator uses an improved average predictive control strategy to enhance the transient response. A 6-b delay-line window ADC with a differential bias circuit is proposed to improve the ADC linearity. An 11-b hybrid DPWM, which consists of a counter and a segmented delay line with a delay-locked loop (DLL), is proposed to relieve the conflict between the die area and DPWM linearity. A prototype of the digital V ² controller IC was fabricated using the 180-nm CMOS process, which was applied to a buck dc–dc switching converter to verify its performance. The experimental results show that an excellent transient response was achieved.

For the exiting neural network (NN)-based controllers, since the training data are not optimized using different control algorithms, their controlling performance improvements are limited. This paper proposes a data-mining-based hardware-efficient NN controller for DC–DC switching converters. Firstly, the data mining strategy for NN controllers is proposed to optimize the training data. In data mining process, the optimal control data are selected from different control algorithms to create an optimized dataset for training NN controller. In addition, to reduce the hardware resources, the structure of a hardware-efficient NN controller is proposed, which comprises coarse-tuning NN (NN-ct) and fine-tuning NN (NN-ft) controllers, and the switching between two NN controllers is conducted based on the output voltage variation. The NN-ct and NN-ft controllers are trained using the optimized fine-tuning and coarse-tuning sub-datasets, respectively. By switching the weights and biases and disabling some hidden-layer nodes, two separate NN controllers can share some hardware resources, thus reducing the hardware cost without sacrificing the performance. The simulation and experimental results demonstrate that data-mining-based NN controller has better performance than other NN controllers. Furthermore, the hardware resource requirement of a hardware-efficient NN controller can be reduced by at least 17% when compared with an ordinary NN controller.

With the continuous development of synthetic aperture radar (SAR) jamming technology, low-power maneuvering repeater jammers are now flexible and can be located on multiple unmanned aerial vehicles (UAVs) and unmanned vehicles (UVs) at the same time, which greatly increases the difficulty of the anti-maneuvering repeater jamming method for spaceborne SAR. Due to the low-power transmission, the locations of the low-power repeater jammers and the protected areas in the imaged swath are relatively close in distance, while the transmission delay of the jamming is approximately equal to the pulse repetition interval (PRI). According to this phenomenon, an anti-maneuvering repeater jamming method using up- and down-chirp modulation is proposed in this paper. After alternately transmitting up- and down-chirp modulation signals, echoes of the jamming and the protected area are recorded in the same location within the echo-receiving window and are related to different chirp modulations. To remove the jamming echoes, de-chirping and frequency filtering are adopted after echo data segmentation. With jamming interference removal using frequency notch filtering, parts of the spectra corresponding to the desired echoes of the imaged swath are simultaneously removed. To recover the unwanted removed range spectra, linear prediction is introduced to improve the focusing quality. Finally, simulation results on both point and distributed targets validate the proposed anti-maneuvering repeater jamming method by using up- and down-chirp modulation.