This paper proposes alternating resistive impedance matching for an impact-type microwind piezoelectric energy harvester (PEH). The proposed PEH is composed of a piezoelectric cantilever and a small wind turbine, which strikes the free end of the cantilever to generate vibrations. The motion of the cantilever is divided into two action periods, impact and vibration, whose optimal resistive loads are different. The impact period detector, in collaboration with a wake-up circuit, identifies the current period and sets the frequency and duty cycle of the oscillator to provide the optimal load for each period. When the cantilever generates energy, the wake-up circuit activates the converter to charge the battery. Otherwise, the circuit goes into sleep mode to save power. The proposed circuit is able to cold start even if the battery is completely drained. Experimental results indicate that the efficiency of the proposed circuit is 70.3% for a wind speed of 1.3 m/s, which is 6.3% higher than that of an existing resistive matching circuit with sleep mode and 7.7% higher than that of a circuit without sleep mode. The proposed circuit is intended for low-speed winds, but it also achieves high efficiency for higher wind speeds.

High-frequency digitally controlled dc–dc switching converters have many advantages, such as very fast transient response and high-power density. However, the studies of control strategies and algorithms specifically for high-frequency digitally controlled dc–dc converters are seldom reported. In this study, we propose a novel digital current-mode controller consisting of both output voltage and inductor current compensators for high-frequency dc–dc switching converters. The voltage compensator is designed based on the delta operator instead of the shift operator, which could improve the control accuracy and reduce hardware costs. Furthermore, the current compensator is designed using an advanced sampling predictive (ASP) control strategy to reduce the requirement of hardware processing speed, and in turn the hardware cost, and to eliminate the influences of noise caused by power switch commutations. Finally, a buck dc–dc switching converter with a switching frequency of 2 MHz is designed and implemented using the proposed digital current-mode controller on a field-programmable gate array (FPGA) platform. Our test results indicate that better control accuracy and lower hardware costs can be realized using the delta operator instead of using the shift operator. In addition, compared with the single digital voltage compensator, the proposed digital current-mode controller has better transient response performances. The control strategy and algorithm proposed in this study are especially effective for digitally controlled high-frequency dc–dc switching converters.

Full-duplex (FD) enables high spectrum efficiency and dynamic spectrum accessing, although its application is restricted by significant self-interference. In this work, we present an integrated, single antenna, wideband FD self-interference suppression front-end solution, targeting for short-range wireless communication. Based on the characteristic of bi-directional signal transparency of N-phase passive mixer, a mixer-first active electrical balance self-interference suppression architecture is proposed. As no costly and space-consuming out-of-chip circulator is needed, compared with traditional single antenna suppression solutions, it is attractive for cost and area saving In addition, to alleviate the multi-path effect, a two-tap baseband self-interference suppression is adopted, which also helps broaden the self-interference suppression bandwidth. The fabricated FD front-end chip, employing 180nm CMOS process, has a noise figure (NF) of 8.6dB, and at the maximum TX power, the NF is degrade by 4.9dB. Test results show the achieved self-interference suppression depth is up to 52dB over 30MHz, with a much smaller antenna interface and chip size which is 0.75 mm $^{2}$ , compared with other dual and signal antenna solutions. The wireless communication function of the propose FD front-end has been verified and the operation carrier frequency range is 0.4-1.2GHz.

Owing to its fast transient response, the V ² control technique for switching converters has wide potential application prospects. In this article, we present a digital V ² controller integrated circuit (IC) for dc–dc switching converters to improve the transient response. The controller IC consists of two compensators and some ancillary circuits, specifically a proportion-integral-differential (PID) compensator and a predictive control compensator, as well as an analog-to-digital converter (ADC) and a digital pulsewidth modulator (DPWM). The PID compensator is designed based on the delta operator instead of the conventional shift operator, which can improve the stability of the converter and reduce hardware costs. The predictive control compensator uses an improved average predictive control strategy to enhance the transient response. A 6-b delay-line window ADC with a differential bias circuit is proposed to improve the ADC linearity. An 11-b hybrid DPWM, which consists of a counter and a segmented delay line with a delay-locked loop (DLL), is proposed to relieve the conflict between the die area and DPWM linearity. A prototype of the digital V ² controller IC was fabricated using the 180-nm CMOS process, which was applied to a buck dc–dc switching converter to verify its performance. The experimental results show that an excellent transient response was achieved.

For the exiting neural network (NN)-based controllers, since the training data are not optimized using different control algorithms, their controlling performance improvements are limited. This paper proposes a data-mining-based hardware-efficient NN controller for DC–DC switching converters. Firstly, the data mining strategy for NN controllers is proposed to optimize the training data. In data mining process, the optimal control data are selected from different control algorithms to create an optimized dataset for training NN controller. In addition, to reduce the hardware resources, the structure of a hardware-efficient NN controller is proposed, which comprises coarse-tuning NN (NN-ct) and fine-tuning NN (NN-ft) controllers, and the switching between two NN controllers is conducted based on the output voltage variation. The NN-ct and NN-ft controllers are trained using the optimized fine-tuning and coarse-tuning sub-datasets, respectively. By switching the weights and biases and disabling some hidden-layer nodes, two separate NN controllers can share some hardware resources, thus reducing the hardware cost without sacrificing the performance. The simulation and experimental results demonstrate that data-mining-based NN controller has better performance than other NN controllers. Furthermore, the hardware resource requirement of a hardware-efficient NN controller can be reduced by at least 17% when compared with an ordinary NN controller.