This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dual-core ARM microprocessor and validated with low-energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross section of the benchmarks tested, even considering the worst case scenario.

A method is presented for automated improvement of embedded application reliability. The compilation process is guided using Genetic Algorithms and a Multi-Objective Optimization Approach (MOOGA). Even though modern compilers are not designed to generate reliable builds, they can be tuned to obtain compilations that improve their reliability, through simultaneous optimization of their fault coverage, execution time, and memory size. Experiments show that relevant reliability improvements can be obtained from efficient exploration of the compilation solutions space. Fault-injection simulation campaigns are performed to assess our proposal against different benchmarks and the results are assessed against a real ARM-based System on Chip under proton irradiation.

Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial replication. This work presents a novel approach for implementing approximate TMR that combines an approximate gate library (ApxLib) with a Multi-Objective Optimization Genetic Algorithm (MOOGA). The algorithm initially performs a blind search, over the huge solution space, optimizing error coverage and area overhead altogether over the next interactions. Experiments compare our approach with a state of the art technique showing an improvement of trade-offs for different benchmark circuits.

This paper presents a fault injection system for performing fault injection campaigns on Commercial-off-the-shelf (COTS) microprocessors. The proposed system takes advantage of the debug facilities of modern microprocessors along with standard GNU Debugger (GDB) for executing and debugging benchmarks. The developed experiments on real boards, as well as on virtual machines, demonstrate the feasibility and flexibility of the proposal as a low-cost solution for assessing the reliability of COTS microprocessors.

This paper presents a technique to mitigate faults induced by radiation in standalone embedded systems based on multi-core processors. To achieve this goal, the well known Modular Redundancy technique has been extended to take advantage of several instruction flows running on different cores. Particularly, results showing softerror mitigation using three instruction flows (threads) are presented in this work. Our technique defines a relaxed lockstep model to synchronize the execution of redundant threads on different cores. Simulated fault injection campaigns were carried out using a multi-core ARM system. The results obtained show that multi-thread versions presents similar or improved protection compared to single-threaded versions, but with reduced performance overhead.