This paper demonstrates the hardware implementation of a recently proposed low-power asynchronous Advanced Encryption Standard substitution box (S-Box) design that is capable of being resistant to side channel attack (SCA). A specified SCA standard evaluation field-programmable gate array (FPGA) board (SASEBO-GII) is used to implement both synchronous and asynchronous S-Box designs. This asynchronous S-Box is based on self-time logic referred to as null convention logic (NCL), which supports a few beneficial properties for resisting SCAs: clock free, dual-rail encoding, and monotonic transitions. These beneficial properties make it difficult for an attacker to decipher secret keys embedded within the cryptographic circuit of the FPGA board. Comparisons on the resistance to SCAs of both the original and proposed S-Box design are presented, using differential power analysis (DPA) and correlation power analysis (CPA) attacks. The power measurement results showed that the NCL S-Box had 22%-26% lower total power consumption than the original and was effective against DPA and CPA attacks. An important factor of successfully implementing DPA or CPA attacks, which is the number of power traces, is also analyzed in this paper.

This work presents the design, hardware implementation, and performance analysis of novel asynchronous AES (advanced encryption standard) Key Expander and Round Function, which offer increased side-channel attack (SCA) resistance. These designs are based on a delay-insensitive (DI) logic paradigm known as null convention logic (NCL), which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR) ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output) analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.

Modern X-ray imaging systems evolve toward digitization for reduced cost, faster time-to-diagnosis, and improved diagnostic confidence. For the digital X-ray systems, charge coupled device (CCD) technology is commonly used to detect and digitize optical X-ray image. This paper presents a novel soft-test/repair approach to overcome the defective pixel problem in CCD-based digital X-ray systems through theoretical modeling and analysis of the test/repair process. There are two possible solutions to cope with the defective pixel problem in CCDs: one is the hard-repair approach and another is the proposed soft-test/repair approach. Hard-repair approach employs a high-yield, expensive reparable CCD to minimize the impact of hard defects on the CCD, which occur in the form of noise propagated through A/D converter to the frame memory. Therefore, less work is needed to filter and correct the image at the end-user level while it maybe exceedingly expensive to practice. On the other hand, the proposed soft-test/repair approach is to detect and tolerate defective pixels at the digitized image level; thereby, it is inexpensive to practice and on-line repair can be done for noninterrupted service. It tests the images to detect the detective pixels and filter noise at the frame memory level and caches them in a flash memory in the controller for future repair. The controller cache keeps accumulating all the noise coordinates and preprocesses the incoming image data from the A/D converter by repairing them. The proposed soft-test/repair approach is particularly devised to facilitate hardware level implementation ultimately for real-time telediagnosis. Parametric simulation results demonstrate the speed and virtual yield enhancement by using the proposed approach; thereby highly reliable, yet inexpensive, soft-test/repair of CCD-based digital X-ray systems can be ultimately realized.

The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of $3.5$ and $4.5$ for the edge detection circuit and multiplication circuit, respectively.

This paper demonstrates a recently proposed low-power side channel attack (SCA) resistant asynchronous S-Box design for the AES crypto-systems. A specified side channel attack standard evaluation FPGA board (SASEBO-GII) is used to implement the design. This board includes two Xilinx FPGAs to perform the cryptographic function and the configuration function separately. This prevents the power trace of the configuration circuit from interfering with the power trace of the cryptographic circuit, so that the measurements of making/resisting power analysis attack can be done fairly. The proposed design is clock free and has flatter power peaks since it is based on a delay-insensitive logic paradigm referred to as null convention logic (NCL). Comparisons between the existing synchronous S-Box design and the proposed asynchronous design are performed in the various aspects; speed, area, total power consumption, and results of differential power analysis (DPA) attack, one of the most powerful cryptanalysis that could extract the secret keys of cryptographic devices. Experimental results shows that the proposed asynchronous S-Box is resistant to DPA attacks and has a lower power consumption than its synchronous counterpart.