Testing and debugging of electrostatic discharge (ESD) or electrical fast transient issues in modern electronic systems can be challenging. The following paper describes the design of an on-chip circuit that detects and stores the occurrence of a fast transient stress event at the ESD protection structures in an input/output pad. Measurements and simulations of a test chip in 90 nm technology show that this circuit can accurately detect and record the presence of a transient stress event with a peak current as low as 0.9 A or a duration as short as 1 ns, and that the detector works well across typical temperature and process variations. The small size of the detector allows it to be used effectively in low-cost commercial integrated circuits. The detector was tested in a system-level environment and successfully records transient events. The importance of simulating with intelligent approximations of the system parasitics is described and demonstrated in measurements. An improved detector is discussed, which performs better in terms of process variations.

The high performance of FPGA (Field Programmable Gate Array) in image processing applications is justified by its flexible reconfigurability, its inherent parallel nature and the availability of a large amount of internal memories. Lately, the Stochastic Computing (SC) paradigm has been found to be significantly advantageous in certain application domains including image processing because of its lower hardware complexity and power consumption. However, its viability is deemed to be limited due to its serial bitstream processing and excessive run-time requirement for convergence. To address these issues, a novel approach is proposed in this work where an energy-efficient implementation of SC is accomplished by introducing fast-converging Quasi-Stochastic Number Generators (QSNGs) and parallel stochastic bitstream processing, which are well suited to leverage FPGA’s reconfigurability and abundant internal memory resources. The proposed approach has been tested on the Virtex-4 FPGA, and results have been compared with the serial and parallel implementations of conventional stochastic computation using the well-known SC edge detection and multiplication circuits. Results prove that by using this approach, execution time, as well as the power consumption are decreased by a factor of $3.5$ and $4.5$ for the edge detection circuit and multiplication circuit, respectively.