A normally-OFF p-GaN gate AlGaN/GaN high-electron-mobility transistor with high ON-state resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) uniformity was realized using a self-terminated digital etching technique. ${R}_{ \mathrm{\scriptscriptstyle ON}}$ uniformity control was improved by simultaneously using an AlN etching stop layer in an epitaxial design and a novel digital etching procedure. Digital etching includes the multiple-cycle oxidation and the wet etching of p-GaN layers and provides easy control of p-GaN removal depth and surface damage reduction at the gate-to-drain and gate-to-source spacing areas. Low-frequency noise and pulse measurements indicated that device surface traps and current collapse phenomena were suppressed.

A metal–insulator–semiconductor p-type GaN gate high-electron-mobility transistor (MIS-HEMT) with an Al₂O₃/AlN gate insulator layer deposited through atomic layer deposition was investigated. A favorable interface was observed between the selected insulator, atomic layer deposition–grown AlN, and GaN. A conventional p-type enhancement-mode GaN device without an Al₂O₃/AlN layer, known as a Schottky gate (SG) p-GaN HEMT, was also fabricated for comparison. Because of the presence of the Al₂O₃/AlN layer, the gate leakage and threshold voltage of the MIS-HEMT improved more than those of the SG-HEMT did. Additionally, a high turn-on voltage was obtained. The MIS-HEMT was shown to be reliable with a long lifetime. Hence, growing a high-quality Al₂O₃/AlN layer in an HEMT can help realize a high-performance enhancement-mode transistor with high stability, a large gate swing region, and high reliability.

This paper reports vertical GaN PN diodes on free-standing (FS) GaN wafer using a complementary metal-oxide-semiconductor (CMOS) compatible contact materials. Static and switching current-voltage (I-V) measurements have been carried out to evaluate the fabricated vertical GaN PN diodes. The vertical GaN PN diode in this work shows turn-on voltage Von of ∼3.3-3.4 V, on/off current ratio of ∼2.7×10⁷, and ideal factor n of ∼2.1. The reverse recovery time Trr is 21.2 ns and 23.2 ns, respectively, under a testing temperature of 300 K and 500K. With an on-state resistance Ron of 3.9 mΩ·cm² and a breakdown voltage VBR of 2.4 kV, this device achieves a power device figure-of-merit (FOM) VBR²/Ron of 1.5×10⁹ V2Ω-1cm¯².

A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (R_on,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the R_on,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower R_on,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (R_on) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its R_on, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated R_on,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

In this paper, a high-current self-aligned double-channel polycrystalline silicon thin-film transistor (SA-DCTFT) is proposed, demonstrated, and analyzed. This self-aligned device, which includes two channels, a nitride spacer, two offset-gated structures, and a raised source/drain (RSD) region, reveals better device performance. In addition, the top and bottom channels of the proposed device are self-aligned, and no extra mask is needed as compared with the conventional double-channel devices. Our experimental results show that the on-current of the SA-DCTFT is about twice higher than that of the conventional structure, and the leakage current and kink effect are considerably reduced simultaneously. Moreover, the device stability, such as threshold voltage shift and current degradation under a high gate bias, is enhanced by the proposed self-aligned double channels, nitride spacer, offset-gated structures, and RSD design. The lower drain electric field of the SA-DCTFT is also benefitted to the device scaling down for better performance.

The surface morphology optimization of ohmic contacts and the Mg out-diffusion suppression of normally off p-GaN gate high-electron-mobility transistors (HEMTs) continue to be challenges in the power electronics industry in terms of the high-frequency switching efficiency. In this study, better current density and reliable dynamic behaviors of p-GaN gate HEMTs were obtained simultaneously by adopting low-temperature microwave annealing (MWA) for the first time. Moreover, HEMTs fabricated using MWA have a higher ION/IOFF ratio and lower gate leakage current than the HEMTs fabricated using rapid thermal annealing. Due to the local heating effect, a direct path for electron flow can be formed between the two-dimensional electron gas and the ohmic metals with low bulges surface. Moreover, the Mg out-diffusion of p-GaN gate layer was also suppressed to maintain good current density and low interface traps.