The proposed study demonstrates a single-step CVD method for synthesizing three-dimensional vertical MoS₂ nanosheets. The postulated synthesizing approach employs a temperature ramp with a continuous N₂ gas flow during the deposition process. The distinctive signals of MoS₂ were revealed via Raman spectroscopy study, and the substantial frequency difference in the characteristic signals supported the bulk nature of the synthesized material. Additionally, XRD measurements sustained the material’s crystallinity and its 2H-MoS₂ nature. The FIB cross-sectional analysis provided information on the origin and evolution of the vertical MoS₂ structures and their growth mechanisms. The strain energy produced by the compression between MoS₂ islands is assumed to primarily drive the formation of vertical MoS₂ nanosheets. In addition, vertical MoS₂ structures that emerge from micro fissures (cracks) on individual MoS₂ islands were observed and examined. For the evaluation of electrical properties, field-effect transistor structures were fabricated on the synthesized material employing standard semiconductor technology. The lateral back-gated field-effect transistors fabricated on the synthesized material showed an n-type behavior with field-effect mobility of 1.46 cm² V⁻¹ s⁻¹ and an estimated carrier concentration of 4.5 × 10¹² cm⁻². Furthermore, the effects of a back-gate voltage bias and channel dimensions on the hysteresis effect of FET devices were investigated and quantified.

In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell MoS2 channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown.

Molybdenum disulfide, a two-dimensional material extensively explored for potential applications in non-von Neumann computing technologies, has garnered significant attention owing to the observed hysteresis phenomena in MoS₂ FETs. The dominant sources of hysteresis reported include charge trapping at the channel–dielectric interface and the adsorption/desorption of molecules. However, in MoS₂ FETs with different channel thicknesses, the specific nature and density of defects contributing to hysteresis remain an intriguing aspect requiring further investigation. This study delves into memristive devices with back-gate modulated channel layers based on CVD-deposited flake-based and thin-film-based MoS₂ FETs, with a few-layer (FL) and thin-film (TF) channel thickness. Analysis of current–voltage ($I-V$) and conductance–frequency ($G_p/\omega -f$) measurements led to the conclusion that the elevated hysteresis observed in TF MoS₂ devices, as opposed to FL devices, stems from a substantial contribution from intrinsic defects within the channel volume, surpassing that of interface defects. This study underscores the significance of considering both intrinsic defects within the bulk and the interface defects of the channel when analyzing hysteresis in MoS₂ FETs, particularly in TF FETs. The selection between FL and TF MoS₂ devices depends on the requirements for memristive applications, considering factors such as hysteresis tolerance and scaling capabilities.

Sufficient energy consumption for conventional information processing makes it necessary to look for new computational methods. One of the possible solutions to this problem is neuromorphic computations using memristive devices. Memristors based on molybdenum disulfide () are a promising way to provide a sizeable amount of hysteresis at low energy costs. Herein, different configurations of memristors as well as the mechanisms involved in hysteresis formation are shown. Bottom gated configuration is beneficial in terms of hysteresis area and energy efficiency. The impact of device channel dimensions on the hysteresis area and energy consumption is discussed. Different operation conditions with triangular, rectangular, sinusoidal, and sawtooth drain‐to‐source pulses are simulated, and rectangular pulses demonstrate the highest energy efficiency. The study shows the potential to realize low‐power neuromorphic systems using memristive devices.