One of the severe issues of the downscaling of semiconductor devices is the threshold voltage reduction which significantly increases the leakage current. Thus, high threshold voltage (HVT) techniques are required to bring down the leakage hike for improved performances. In this paper, for the first time, we investigate the analog/radio frequency (RF) and linearity performances of silicon (Si) FinFET by employing HVT techniques. Using well-calibrated technology computer aided design models, to mitigate the leakage current, we analyzed the following approach to get HVT: (a) increasing channel doping (N _ch′); (b) making drain-side underlap (L _dsu); (c) increasing gate length (L _g′). Two flavors of fin field effect transistors (FinFETs) viz bulk and silicon-on-insulator (SOI) are suitably compared over their baseline counterpart, i.e. without HVTs. A thorough investigation of analog/RF metrics such as transconductance, output resistance, gate capacitance, cut-off frequency, gain-bandwidth, and transconductance-frequency product proves the eminence of bulk-FinFET over its peer SOI-FinFET. In contrast, SOI-FinFET shows merits in intrinsic gain and linearity such as g _m2, g _m3, VIP₂, VIP₃, IIP₃, IMD₃, and 1 dB compression point. Thus, HVT techniques are worth analyzing for a FinFET architecture employed in analog/RF applications.

In this paper, polarization-graded AlGaN back-barrier nanolayer has been introduced to improve the DC and RF parameters of gallium nitride-based high electron mobility transistors (HEMT). To explore the characteristics, both graded and non-graded double heterojunction high electron mobility transistor (DH-HEMT) structures are optimized using SILVACO-ATLAS physical simulator. Enhanced DC and RF parameters have been observed in the optimized graded DH-HEMT. In this paper, we have also studied the development of the quantum wells at the AlGaN/GaN interfaces due to the conduction band discontinuity in both structures.

łabelABPhase transition FinFET (PT-FinFET) is an emerging steep slope device that utilizes phase transition material (PTM) at the source of the host FinFET to achieve steep switching and boost Ion/Ioff ratio compared to conventional transistors. Due to nonzero ρ_MET of the assisting PTM, PT-FinFET suffers from low Ion as compared to baseline FinFET. To address this issue, we propose, analyze, and mathematically justify a device design exhibiting enhanced subthreshold swing (SS), Ion and Ioff by exploiting a negative capacitance material at the gate of the PT-FinFET. In the proposed model, critical thickness (tfe) of 3 nm for negative capacitance material was achieved. In comparison with the baseline FinFET and negative capacitance PT-FinFET, the proposed device (NC-PT-FinFET) is able to improve Ion/Ioff ratio by 3.02 and 2.94 decades, respectively. Furthermore, SS of nearly 10 mV/decade is achieved over 4 decades of drain current with minimum value of 6.8 mV/decade for tfe = 3 nm.