This paper presents an innovative and automated measurement setup for the characterization of variability effects in CMOS transistors using array-based integrated circuits (ICs), through which a better understanding of CMOS reliability could be attained. This setup addresses the issues that come with the need for a trustworthy statistical characterization of these effects: testing a very large number of devices accurately but, also, in a timely manner. The setup consists of software and hardware components that provide a user-friendly interface to perform the statistical characterization of CMOS transistors. Five different electrical tests, comprehending time-zero and time-dependent variability effects, can be carried out. Test preparation is, with the described setup, reduced to a few seconds. Moreover, smart parallelization techniques allow reducing the typically time-consuming aging characterization from months to days or even hours. The scope of this paper thus encompasses the methodology and practice of measurement of CMOS time-dependent variability, as well as the development of appropriate measurement systems and components used in efficiently generating and acquiring the necessary electrical signals.

With tightening reliability margins, product-level aging analysis is gradually gaining impetus and is set to become an integral part of the modern design flow. Increased emphasis is placed on the development of physics-based compact models for the phenomena responsible for transistor degradation and their integration into EDA environments. Commercial Process Design Kits (PDKs) of advanced technologies have also started to include compact models for transistor degradation along with a dedicated reliability simulation framework. In this work, we present a comprehensive study of the compact aging models in one such commercial PDK, with the help of extensive measurement data from individual devices as well as Ring Oscillators (RO). Then, we perform our own extraction of model parameter shifts from full Id-Vgs fitting of the measured BTI-stressed devices to gain insight into the modeling procedure adopted by the foundry. We finally use the parameters extracted thusly to investigate the impact of the time-0 and the time-dependent device-to-device variability on RO degradation.

This paper presents a toolbox for the automation of the electrical characterization of CMOS transistors. The developed software provides a user-friendly interface to carry out different tests to evaluate time-zero (i.e., process) and time-dependent variability in CMOS devices. Also, the software incorporates a post-processing capability that allows users to visualize the data. Moreover, without loss of generality, the toolbox allows the user, from the measured data, to feed a particular physics-based model that accounts for various aging phenomena.

This work reports an on-chip heater structure fabricated in the Front End of Line (FEOL) on a versatile ring-oscillator (RO) array utilized to conduct statistical characterization of on-chip annealing of statically, i.e., Bias Temperature Instabilities (BTI), and dynamically, i.e., BTI-Hot Carrier Degradation (HCD), stressed ROs. The heater allows to reach local temperatures up to $\Delta \text {T} = +{300}^{\circ }\text{C}$ in milliseconds. Accurate thermal modelling of the heater structure has been conducted demonstrating that the heat is homogenously distributed across the array area, resulting in a valuable tool for precise on-chip circuit anneal. Exploiting the on-chip heater features, sequential annealing tests with increasing duration have been conducted after accelerated degradation of RO circuits. Moreover, we report detailed relaxation maps that allow a thorough insight into the annealing behaviour of our circuits vs temperature and time. This can potentially be used to anneal ICs “on-line” to prolong their useful lifetime towards a more sustainable use.

In this work, a CMOS transistor array is presented, which allows performing process variability, Random Telegraph Noise and BTI/CHC aging characterization in a single chip. The array, called ENDURANCE, integrates 3136 MOS transistors, for single and massive electrical testing. This chip, together with a dedicated measurement set-up, allows programming any of these electrical tests, considerably reducing the total time needed for aging measurements by using a parallelization technique.