The ubiquity of threshold voltage relaxation is demonstrated in samples with both conventional and high-k dielectrics following various stress conditions. A technique based on recording short traces of relaxation during each measurement phase of a standard measure-stress-measure sequence allows monitoring and correcting for the otherwise-unknown relaxation component. The properties of relaxation are discussed in detail for pFET with SiON dielectric subjected to NBTI stress. Based on similarities with dielectric relaxation, a physical picture and an equivalent circuit are proposed.

Broad similarity between negative bias temperature instability (NBTI) relaxation and 1/f noise is observed. Individual transitions in NBTI relaxation in small pFETs are observed and Poisson defect number statistics is inferred. Finally, it is argued that the wide distribution of defect times should be considered in addition to defect number variation in small devices.

A new method for the characterization of random telegraph signals (RTSs) is presented. The method, which is based on the time lag plot, is illustrated using Monte Carlo generated RTS traces and applied to identify the contribution of defects in multilevel RTS measured in a pMOS transistor. The results show that the new method provides a powerful and easily implementable technique to obtain the parameters of the defects responsible of multilevel RTS, even when the background noise is relevant.

A new Negative Bias Temperature Instability (NBTI) model based on the probability of charge/discharge of defects in devices is presented. The model correctly describes the main experimental NBTI features, such as the threshold voltage shift (ΔV _T ) evolution under DC or AC stresses, its frequency and duty cycle dependence and the statistical ΔV _T distribution in small transistors. Finally, the model is used to explain the dependence of NBTI degradation on the stress/relaxation times, frequency and duty cycle in terms of defect occupancy.

With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.