Time-series classification (TSC) is a challenging problem in machine learning and significant efforts have been made to improve its speed and computation efficiency. Among various approaches, dynamic time warping (DTW) algorithm is one of the most prevalent methods for TSC due to its succinctness and generality. To improve the throughput of the operation, this work presents a mixed-signal DTW accelerator utilizing mixed-signal time-domain (TD) computing where signals are encoded and processed using time pulses. A pipelined operation is enabled by a specially designed time flip-flop (TFF) circuit leading to dramatic improvements in performance and scalability of the operation. A 65-nm CMOS test chip was implemented and measured. The results show more than $9\times $ improvements in throughput compared with prior work on TSC. As most existing TD designs suffer from the lack of TD storage elements, this work utilizes sequential circuit elements in TD computing extending the capability of time-based circuits.

While neural network (NN) accelerators are being significantly developed in recent years, CPU is still essential for data management and pre-/post-processing of accelerators in a commonly used heterogeneous architecture, which usually contains an NN accelerator and a processor core with data transfer performed by direct memory access (DMA) engine. This work presents a special neural processor, referred to as a systolic neural CPU processor (SNCPU), which is a unified architecture combining deep learning and general-purpose computing for fifth-generation of reduced instruction set computer (RISC-V) to improve end-to-end performance for machine learning (ML) tasks compared with a common heterogeneous architecture with CPU and accelerator. With 64%–80% processing elements (PEs) logic reuse and 10% area overhead, SNCPU can be configured into ten RISC-V CPU cores. Special bi-directional dataflow and four different working modes are developed to enhance the utilization of deep NN (DNN) accelerator and eliminate the expensive data transfer between CPU and DNN accelerator in existing heterogeneous architecture. A 65-nm test chip was fabricated demonstrating a 39%–64% performance improvement on end-to-end image classification tasks for ImageNet, Cifar10, and MNIST datasets with over 95% PE utilization and up to 1.8TOPs/W power efficiency.

A low power switched decoupling capacitor circuit is proposed to suppress on-chip resonant supply noise. Compared to previous analog techniques, the proposed digital implementation achieves a 9X reduction in quiescent power with improved tolerance to PVT variation and tuning capability for optimal switching threshold. Measurements from a 0.13μm test chip show an 11X boost in effective decap value and a 9.8dB suppression in resonant supply noise by using the proposed circuit.

This paper presents a fully integrated buck regulator design for low-power applications. In order to enable the usage of on-chip inductor for low load current 10-40 mA, the proposed buck regulator is designed with an ultra-high switching frequency at 2 GHz, which is the highest switching frequency reported so far. To reduce the power switch losses, resonant switching scheme is utilized to save the switching clock energy. Tunable slew rate recovery circuits are used to improve the efficiency of the design. The proposed buck regulator has been implemented in 65-nm CMOS technology with a 1.1-V input. Measurement shows a wide output range of 0.3-0.86 V. The proposed design achieves up to 73% power efficiency.