Stochastic computing (SC) is a promising technique for applications that require low area overhead and fault tolerance, but can tolerate relatively high latency. In the SC paradigm, logical computation is performed on randomized bit streams. In prior work, streams were generated with linear feedback shift registers; these contributed heavily to the hardware cost and consumed a significant amount of power. This paper introduces a new approach for encoding signal values: computation is performed on analog periodic pulse signals. Exploiting pulse width modulation, time-encoded signals corresponding to specific values are generated by adjusting the frequency and duty cycles of pulse width modulated (PWM) signals. With this approach, the latency, area, and energy consumption are all greatly reduced. Experimental results on image processing applications show up to 99% performance speedup, 98% saving in energy dissipation, and 40% area reduction compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy-efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.

Analog designs consist of multiple hierarchical functional blocks. Each block can be built using one of several design topologies, where the choice of topology is based on circuit performance requirements. A major challenge in automating analog design is in the identification of these functional blocks, which enables the creation of hierarchical netlist representations. This can facilitate a variety of design automation tasks, such as circuit layout optimization, because the layout is dictated by constraints at each level, such as symmetry requirements, that depend on the topology of the hierarchical block. Traditional graph-based methods find it hard to automatically identify the large number of structural variants of each block. To overcome this limitation, this article leverages recent advances in graph neural networks (GNNs). A variety of GNN strategies is used to identify netlist elements for circuit functional blocks at higher levels of the design hierarchy, where numerous design variants are possible. At lower levels of hierarchy, where the degrees of freedom in circuit topology is limited, structures are identified using graph-based algorithms. The proposed hierarchical recognition scheme enables the identification of layout constraints, such as symmetry and matching, which enable high-quality hierarchical layouts. This method is scalable across a wide range of analog designs. An experimental evaluation shows a high degree of accuracy over a wide range of analog designs, identifying functional blocks, such as low-noise amplifiers, operational transconductance amplifiers, mixers, oscillators, and band-pass filters, in larger circuits.

A continuous-time multiple-input multiple-output crosstalk cancellation (MIMO-XTC) architecture operating at 2-6 Gb/s has been proposed. The performance of the XTC equalizer has been measured with various spacings of FR4 channels and data rates. The crosstalk energy reutilization technique efficiently handles crosstalk and achieves high signal integrity in severe crosstalk environments where crosstalk had completely closed the data eye. Measurement results show improvement in jitter_{p- p} and vertical opening of the eye diagram by 67% UI and 58.2%, respectively, which is the best known improvement to date. The MIMO-XTC portion occupies 0.03 mm² and consumes 2.8 mW/Gbps/lane, which is two times lower than previously proposed XTC schemes.

This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL) power. A single coarse counter logic structure along with time-interleaved even/odd paths significantly reduces the complexity and speed of the TDC logic. The proposed TDC consumes only 0.44 to 24 mW for 0.077 to 24.42 ns of detection range. The multi-path GRO accelerates the oscillation speed and achieves approximately 6.2 ps of time resolution. The GRO-TDC shows -1.43 to 1.35 least-significant bits (LSB) of differential non-linearity (DNL) and -1.32 to 1.96 LSB of integral non-linearity (INL) over a 11-bit dynamic range (DR). The entire ADPLL including the proposed TDC has been fabricated in a 65 nm CMOS process and occupies 0.67 mm2 of active area. The prototype ADPLL consumes 12.22 mW from 1.2 V supply and the TDC consumes only 0.65 mW for a 50-phase offset code. A modified integrating structure in the subsequent digital loop filter (DLF) has been developed to mitigate dithering noise on Vctrl code and the measured reference spur is -69.38 dBc at 3.6 GHz center frequency. The tuning range of the implemented ADPLL is 3.5 to 4.7 GHz by using 2-bit band switching and 5-bit coarse control, while maintaining low-KDCO values to suppress in-band quantization noise. The measured root-mean-square (RMS) jitter is 0.94 ps and 0.99 ps at 3.6 GHz integer-mode and 3.60743 GHz fractional-mode respectively.

In this paper, we have developed simplified analytical models for far-end crosstalk that points us in a direction to an ultra-low power technique for reducing crosstalk-induced jitter in existing high-speed memory I/O interfaces. This new architecture design introduces variable delays in alternating lines at the transmitter to mitigate crosstalk-induced jitter. The power-efficient technique decreases jitter at the expense of lowering the voltage margin. The architecture has been verified via simulations and direct measurements. Simulation results at 12 Gb/s show that staggered I/Os can successfully reduce jitter by 66.7% and widen the eye by 15.0% while only degrading the voltage margin by 19.5%. Measurement results obtained at 600 Mb/s confirm the presented theoretical framework and show the removal of CIJ at the expense of decreasing the voltage margin from 373 mV to 215 mV.